Received-SPF: pass (google.com: domain of linux-kernel+bounces-78711-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
From: "ni.liqiang" <ni_liqiang@126.com>
To: will@kernel.org,
	danielmentz@google.com
Cc: iommu@lists.linux.dev,
	jin.qi@zte.com.cn,
	joro@8bytes.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	ni.liqiang@zte.com.cn,
	niliqiang.io@gmail.com,
	robin.murphy@arm.com
Subject: Re: [PATCH] drivers/iommu: Ensure that the queue base address is successfully written during SMMU initialization.
Date: Sat, 24 Feb 2024 00:20:10 +0800
Message-Id: <20240223162010.6884-1-ni_liqiang@126.com>
In-Reply-To: <20240221160849.GB7362@willie-the-truck>
References: <20240221160849.GB7362@willie-the-truck>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

> (Disclaimer: I don't know what a CCG port is)

CCG(CXL Gateway) is a part of the CMN700 Coherent Mesh Network. It plays
a crucial role in facilitating cross-die access in a multi-chip system.

> Hmmm. The part that doesn't make sense to me here is that migrating between
> CPUs implies context-switching, and we have a DSB on that path in
> __switch_to(). So why would adding barriers to the driver help? Maybe it
> just changes the timing?

This is very likely. Through our experiments, adding a delay before CMDQEN
does not reproduce the failure of writing to the CMDQ base register.

> I'm not sure what you're proposing, but I don't think Linux should be
> changed to accomodate this.

I am very grateful for the responses from both of you experts. We will
continue to check the current hardware configuration of the system
and attempt to fix this issue.
Once again, I express my thanks. Thank you.