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From: Jernej =?utf-8?B?xaBrcmFiZWM=?= <jernej.skrabec@gmail.com>
To: =?utf-8?B?T25kxZllag==?= Jirman <megi@xff.cz>,
 Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
 Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
 Thomas Zimmermann <tzimmermann@suse.de>, David Airlie <airlied@gmail.com>,
 Daniel Vetter <daniel@ffwll.ch>, Samuel Holland <samuel@sholland.org>,
 dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org,
 linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
 Jernej =?utf-8?B?xaBrcmFiZWM=?= <jernej.skrabec@gmail.com>
Subject: Re: [PATCH 3/3] drm/sun4i: Fix layer zpos change/atomic modesetting
Date: Sat, 24 Feb 2024 08:10:05 +0100
Message-ID: <6018948.lOV4Wx5bFT@archlinux>
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On Saturday, February 24, 2024 3:20:43 AM CET Ond=C5=99ej Jirman wrote:
> On Thu, Feb 22, 2024 at 09:02:53PM +0100, Jernej =C5=A0krabec wrote:
> > Dne sreda, 21. februar 2024 ob 14:45:20 CET je Maxime Ripard napisal(a):
> > > Hi,
> > >=20
> > > On Fri, Feb 16, 2024 at 08:04:26PM +0100, Ond=C5=99ej Jirman wrote:
> > > > From: Ondrej Jirman <megi@xff.cz>
> > > >=20
> > > > Identical configurations of planes can lead to different (and wrong)
> > > > layer -> pipe routing at HW level, depending on the order of atomic
> > > > plane changes.
> > > >=20
> > > > For example:
> > > >=20
> > > > - Layer 1 is configured to zpos 0 and thus uses pipe 0. No other la=
yer
> > > >   is enabled. This is a typical situation at boot.
> > > >=20
> > > > - When a compositor takes over and layer 3 is enabled,
> > > >   sun8i_ui_layer_enable() will get called with old_zpos=3D0 zpos=3D=
1, which
> > > >   will lead to incorrect disabling of pipe 0 and enabling of pipe 1.
> > > >=20
> > > > What happens is that sun8i_ui_layer_enable() function may disable
> > > > blender pipes even if it is no longer assigned to its layer.
> > > >=20
> > > > To correct this, move the routing setup out of individual plane's
> > > > atomic_update into crtc's atomic_update, where it can be calculated
> > > > and updated all at once.
> > > >=20
> > > > Remove the atomic_disable callback because it is no longer needed.
> > > >=20
> > > > Signed-off-by: Ondrej Jirman <megi@xff.cz>
> > >=20
> > > I don't have enough knowledge about the mixers code to comment on your
> > > patch, so I'll let Jernej review it. However, this feels to me like t=
he
> > > pipe assignment is typically the sort of things that should be dealt
> > > with device-wide, and in atomic_check.
> >=20
> > In DE2 and DE3.0, you cannot move planes between mixers (crtcs), becaus=
e each
> > one is hardwired to specific mixer. Movable planes are the feature of D=
E3.3
> > and one of the pain points for upstreaming the code. Anyway, this commi=
t only
> > addresses current issue of enabling and disabling planes and handling z=
pos.
> >=20
> > In atomic check you can only precalculate final register values, but I =
don't
> > see any benefit doing that. I think that this code elegantly solves cur=
rent
> > issue of enabling or disabling wrong plane in certain situations, so:
> >=20
> > Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> >=20
> > Note, if there is new revision, please rewrite blender regmap_update_bi=
ts()
> > to regmap_write(). Since there is HW issue with reads, I would like to
> > get rid of regmap_update_bits() calls eventually.
>=20
> I've looked into it and I can probably rewrite these quite readily:
>=20
> +	regmap_update_bits(mixer->engine.regs,
> +			   SUN8I_MIXER_BLEND_ROUTE(bld_base),
> +			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(0) |
> +			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(1) |
> +			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(2) |
> +			   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(3),
> +			   route);
>=20
> The mask here covers all implemented bits in the register.
>=20
> +	regmap_update_bits(mixer->engine.regs,
> +			   SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
> +			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(0) |
> +			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(1) |
> +			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(2) |
> +			   SUN8I_MIXER_BLEND_PIPE_CTL_EN(3),
> +			   pipe_en);
> +
>=20
> The mask here doesn't cover BLD_FILL_COLOR_CTL.Px_FCEN bits that implemen=
t solid
> color filling. But those can be 0 anyway except for pipe0 which is hardco=
ded by
> the driver to 1, I think:
>=20
> 631         /*
> 632          * Set fill color of bottom plane to black. Generally not nee=
ded
> 633          * except when VI plane is at bottom (zpos =3D 0) and enabled.
> 634          */
> 635         regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(b=
ase),
> 636                      SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));

Correct on all counts. That's what I've meant.

>=20
> I will not be able to get rid of regmap_update_bits in sun8i_layer_enable
> because that register there has other important things in it like framebu=
ffer
> pixel format, etc.

Yeah, this rework would certainly be more involved, so it's out of the scop=
e of
this series.

Best regards,
Jernej

>=20
> kind regards,
> 	o.
>=20
> > Best regards,
> > Jernej
> >=20
> > >=20
> > > If I'm talking non-sense, it would be great to mention at least why t=
hat
> > > can't be an option in the commit log.
> > >=20
> > > Maxime
> > >=20
> >=20
> >=20
> >=20
> >=20
>=20