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From: Yang Xiwen via B4 Relay <devnull+forbidden405.outlook.com@kernel.org>
Subject: [PATCH RFC 0/2] clk: hisilicon: add support for PLL
Date: Sun, 25 Feb 2024 00:56:08 +0800
Message-Id: <20240225-pll-v1-0-fad6511479c6@outlook.com>
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To: Michael Turquette <mturquette@baylibre.com>, 
 Stephen Boyd <sboyd@kernel.org>
Cc: David Yang <mmyangfl@gmail.com>, 
 Igor Opaniuk <igor.opaniuk@foundries.io>, 
 Jorge Ramirez-Ortiz Gmail <jorge.ramirez.ortiz@gmail.com>, 
 linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, 
 Yang Xiwen <forbidden405@outlook.com>
Reply-To: <forbidden405@outlook.com>

HiSilicon PLLs are used by various SoCs to provide variable clocks for
various system on the SoC.

Hi3559 has implemented their own PLL driver. Also fix name duplication
because of that.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
Yang Xiwen (2):
      clk: hisilicon: rename hi3519 PLL registration function
      clk: hisilicon: add support for PLL

 drivers/clk/hisilicon/Makefile      |   2 +-
 drivers/clk/hisilicon/clk-hi3559a.c |   4 +-
 drivers/clk/hisilicon/clk-pll.c     | 171 ++++++++++++++++++++++++++++++++++++
 drivers/clk/hisilicon/clk.c         |  24 +++++
 drivers/clk/hisilicon/clk.h         |  12 +++
 5 files changed, 210 insertions(+), 3 deletions(-)
---
base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d
change-id: 20240225-pll-2653677c5e1d

Best regards,
-- 
Yang Xiwen <forbidden405@outlook.com>