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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708805156; c=relaxed/simple; bh=VVconFov6r58LkpENTvrOORG9jm8Kbr70JfM/2Cn400=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=rmUNQQpxRxRNzTv3M9t4EKRZqMhw9Ljc1yN3xO/Gxl5rtglybKMyulRAjXVo8Lg7b8Nx2eNvjfdvF0aMjqVsNZkEAcVj46Guo9DFarWpinaF3k4+5ketWCdWRd5V07TqaooF7m9TS9KJ1tIgcNYnixMHPimu1pMAYvXWBwh7CyA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SLaoaovN; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4ADAFC433F1; Sat, 24 Feb 2024 20:05:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708805155; bh=VVconFov6r58LkpENTvrOORG9jm8Kbr70JfM/2Cn400=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=SLaoaovNXKUTSsxYBUgHNut8hVCCfzputtDm/gpygPrfTPJm8FuHZBj61UBkJIW12 90TYHeBju39F35cqBrQFPy6vySRRKJTtcPZJwzjOe2RxJw9SD2p3ROifYB6k7UE/h5 xwxeF+ev7DF3HS0Vf/U8mEtNVu4oUG/HWgenWkOpdzM0pQvf5FX3v8CAc+ojAiF/OK pA9OOu5IrBXZ1xy3ms2MkXKdVC8vy5UZw5TKr8r0LIXlyIYYRod31jzXvv5cGnzmoW lFmajO2lCcwvPCLs/Nw6nU68GV7uZq2l7s2/MaKoHtgS1Q+QG+SrzRY5xAA6hLYc7M cShERKkqiaSRw== Date: Sat, 24 Feb 2024 20:05:51 +0000 From: Conor Dooley To: Varshini Rajendran Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 21/39] dt-bindings: clk: at91: add sam9x7 Message-ID: <20240224-procreate-tumble-52241e198587@spud> References: <20240223171342.669133-1-varshini.rajendran@microchip.com> <20240223172732.672645-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="7iwFKyEFd0qR+fSs" Content-Disposition: inline In-Reply-To: <20240223172732.672645-1-varshini.rajendran@microchip.com> --7iwFKyEFd0qR+fSs Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Feb 23, 2024 at 10:57:32PM +0530, Varshini Rajendran wrote: > Add bindings for SAM9X7's slow clock controller. >=20 > Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley Cheers, Conor. > --- > Changes in v4: > - Added sam9x7 compatible as an enum with sama7g5 compatible as per the > review comment > --- > .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) >=20 > diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sck= c.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml > index 7be29877e6d2..ab81f0b55ad5 100644 > --- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml > +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml > @@ -18,7 +18,9 @@ properties: > - atmel,sama5d4-sckc > - microchip,sam9x60-sckc > - items: > - - const: microchip,sama7g5-sckc > + - enum: > + - microchip,sama7g5-sckc > + - microchip,sam9x7-sckc > - const: microchip,sam9x60-sckc > =20 > reg: > --=20 > 2.25.1 >=20 --7iwFKyEFd0qR+fSs Content-Type: application/pgp-signature; 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