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AJvYcCVj2bPfV2qW001YsJkzeEZhF5HOVXTXFqeFxW791ZO+NC+4VknE2u/VDumSsmbK+9PdQZXJsI27Ky77dd9OvfsuMOGHkE2hG6EFMnWW X-Gm-Message-State: AOJu0YwD2z4gh20RQZkcEG5tkB0H3N0k1xqgZLiFGz/rDPOq08Okug3Y q8KVAH2gdI1HQY2xQn4eVm0YXyjC6F17RpQ1m3IV4suECYZWNCusneaxb0zA8aA= X-Received: by 2002:a2e:990b:0:b0:2d2:7164:c6ba with SMTP id v11-20020a2e990b000000b002d27164c6bamr2529804lji.43.1708877474757; Sun, 25 Feb 2024 08:11:14 -0800 (PST) Received: from [127.0.1.1] ([178.197.222.116]) by smtp.gmail.com with ESMTPSA id n21-20020a2e7215000000b002d2697570fcsm579184ljc.93.2024.02.25.08.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 08:11:14 -0800 (PST) From: Krzysztof Kozlowski To: Sylwester Nawrocki , Chanwoo Choi , Sam Protsenko Cc: Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tomasz Figa , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org In-Reply-To: <20240224202053.25313-13-semen.protsenko@linaro.org> References: <20240224202053.25313-1-semen.protsenko@linaro.org> <20240224202053.25313-13-semen.protsenko@linaro.org> Subject: Re: (subset) [PATCH v3 12/15] clk: samsung: Add CPU clock support for Exynos850 Message-Id: <170887747270.215710.14391018888369319254.b4-ty@linaro.org> Date: Sun, 25 Feb 2024 17:11:12 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.12.4 On Sat, 24 Feb 2024 14:20:50 -0600, Sam Protsenko wrote: > Implement CPU clock control for Exynos850 SoC. It follows the same > procedure which is already implemented for other SoCs in clk-cpu.c: > > 1. Set the correct rate for the alternate parent (if needed) before > switching to use it as the CPU clock > 2. Switch to the alternate parent, so the CPU continues to get clocked > while the PLL is being re-configured > 3. Adjust the dividers for the CPU related buses (ACLK, ATCLK, etc) > 4. Re-configure the PLL for the new CPU clock rate. It's done > automatically, as the CPU clock rate change propagates to the PLL > clock, because the CPU clock has CLK_SET_RATE_PARENT flag set in > exynos_register_cpu_clock() > 5. Once the PLL is locked, set it back as the CPU clock source > 6. Set alternate parent clock rate back to max speed > > [...] Applied, thanks! [12/15] clk: samsung: Add CPU clock support for Exynos850 https://git.kernel.org/krzk/linux/c/61f4399c74d0677ee64e42f7b8d4ab01ee39de45 Best regards, -- Krzysztof Kozlowski