Date: Tue, 1 Jan 2008 22:42:41 +0100
From: Christer Weinigel <christer@weinigel.se>
To: Ingo Molnar <mingo@elte.hu>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>, "David P. Reed" <dpreed@reed.com>,
       "H. Peter Anvin" <hpa@zytor.com>, Rene Herman <rene.herman@gmail.com>,
       Paul Rolland <rol@as2917.net>, Pavel Machek <pavel@ucw.cz>,
       Thomas Gleixner <tglx@linutronix.de>, linux-kernel@vger.kernel.org,
       Ingo Molnar <mingo@redhat.com>, rol@witbe.net
Subject: Re: [PATCH] x86: provide a DMI based port 0x80 I/O delay override.
Message-ID: <20080101224241.2ce431bd@weinigel.se>
In-Reply-To: <20080101210143.GB759@elte.hu>
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On Tue, 1 Jan 2008 22:01:43 +0100
Ingo Molnar <mingo@elte.hu> wrote:

> > out 80h, al is only two bytes.  Any alternative that has been 
> > suggested in this discussion will use more space.  mov dx,
> > alt_port; out dx, al will be larger, a function call will
> > definitely be a lot larger. People have been making changes to the
> > kernel to save a couple of hundred bytes of text size.
> 
> i've done dozens of patches that saved much less of text size, so
> yes, i very much care about code size. But it has been stated in this
> thread that most of the _p() API uses in the kernel today are bogus.
> So eventually getting rid of the bogus ones will be a net code size 
> _reduction_. (But even that is besides the point, we prefer clean and 
> easier to maintain code.)

And once again, the _p in the code that talks to the PIT is very much
non-bogus.  And it is a critical path that's called a lot.  The i8253
PIT and the i8259 interrupt controller are probably the only ones that
are relevant on a modern machine, and it seems that even some fairly
modern chipsets have limitations on how fast you can drive them.

BTW, I just checked the Intel M8253 data sheet (dead tree variant), and
it says under A.C Characteristics, READ CYCLE:

    Recovery Time Between /READ and Any Other Control Signal: 1 us

So at least for the original M8253 a udelay(1) might be more
appropriate than outb_p, since the delay is not expressed in clock
cycles but absolute time.

The data sheet for the Intel M8259A says:

    End of /RD to Next Command: 300 ns
    End of /WR to Next Command: 370 ns

On the other hand, I don't know how all the i8253/i8259 clones or the
numerous variants of Super I/O chips behave.  It wouldn't surprise me
if some Super I/O chip uses the ISA bus clock to latch the values
internally so that the delay is dependent on the bus frequency instead.

> > I don't know if the difference in code size or the udelay will be 
> > significantly slower, but I think it might be.
> 
> ok, "I dont know but it might be slower" is a perfectly fine
> statement instead of your original "it will be slower".

I didn't say that, I said I'm afraid it will be slower. :-)

  /Christer
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