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Mon, 26 Feb 2024 09:59:16 GMT Received: from [10.201.2.96] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 26 Feb 2024 01:59:12 -0800 Message-ID: <3c1b3102-1817-4211-8d9a-aa56d05d7e6a@quicinc.com> Date: Mon, 26 Feb 2024 15:29:09 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset Content-Language: en-US To: Gabor Juhos , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Gokul Sriram Palanisamy" , Varadarajan Narayanan , Sricharan Ramabadhran CC: , , References: <20240225-gcc-ipq5018-register-fixes-v1-0-3c191404d9f0@gmail.com> <20240225-gcc-ipq5018-register-fixes-v1-3-3c191404d9f0@gmail.com> From: Kathiravan Thirumoorthy In-Reply-To: <20240225-gcc-ipq5018-register-fixes-v1-3-3c191404d9f0@gmail.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 5in7-8T2oh3cMbMIYNrRhgewU0-869Ov X-Proofpoint-GUID: 5in7-8T2oh3cMbMIYNrRhgewU0-869Ov X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_07,2024-02-23_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 suspectscore=0 spamscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402260075 On 2/25/2024 11:02 PM, Gabor Juhos wrote: > The current register offset used for the GCC_UBI0_AXI_ARES reset > seems wrong. Or at least, the downstream driver uses [1] the same > offset which is used for other the GCC_UBI0_*_ARES resets. > > Change the code to use the same offset used in the downstream > driver and also specify the reset bit explicitly to use the > same format as the followup entries. > > 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L3773 Reviewed-by: Kathiravan Thirumoorthy > > Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") > Signed-off-by: Gabor Juhos > --- > drivers/clk/qcom/gcc-ipq5018.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c > index 5e81cfa77293a..e2bd54826a4ce 100644 > --- a/drivers/clk/qcom/gcc-ipq5018.c > +++ b/drivers/clk/qcom/gcc-ipq5018.c > @@ -3632,7 +3632,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = { > [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 }, > [GCC_TCSR_BCR] = { 0x28000, 0 }, > [GCC_TLMM_BCR] = { 0x34000, 0 }, > - [GCC_UBI0_AXI_ARES] = { 0x680}, > + [GCC_UBI0_AXI_ARES] = { 0x68010, 0 }, > [GCC_UBI0_AHB_ARES] = { 0x68010, 1 }, > [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 }, > [GCC_UBI0_DBG_ARES] = { 0x68010, 3 }, >