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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Mon, 26 Feb 2024 14:00:20 +0000
Message-ID: <CA+V-a8uNaRL7wE0SmwmiCq3o798-2Kd-fegKJ2Tep5mZuS2O2w@mail.gmail.com>
Subject: Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P}
 System Controller
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, 
	linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Geert,

Thank you for the review.

On Mon, Feb 26, 2024 at 1:41=E2=80=AFPM Geert Uytterhoeven <geert@linux-m68=
k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Mon, Feb 19, 2024 at 5:10=E2=80=AFPM Prabhakar <prabhakar.csengg@gmail=
com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add DT binding documentation for System Controller (SYS) found on
> > RZ/V2H{P} ("R9A09G057") SoC's.
>
> RZ/V2H(P)
>
> >
> > SYS block contains the SYS_LSI_DEVID register which can be used to
> > retrieve SoC version information.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-s=
ys.yaml
> > @@ -0,0 +1,59 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.y=
aml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/V2H{P} System Controller (SYS)
> > +
> > +maintainers:
> > +  - Geert Uytterhoeven <geert+renesas@glider.be>
> > +
> > +description:
> > +  The RZ/V2H{P} SYS (System Controller) controls the overall
>
> RZ/V2H(P)
>
OK.

> > +  configuration of the LSI and supports the following functions,
> > +  - Trust zone control
> > +  - Extend access by specific masters to address beyond 4GB space
> > +  - GBETH configuration
> > +  - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC=
/TSU
> > +  - LSI version
> > +  - WDT stop control
> > +  - General registers
> > +
> > +properties:
> > +  compatible:
> > +    const: renesas,r9a09g057-sys
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: Clock from external oscillator
>
> Isn't this SYS_0_PCLK inside the CPG?
>
As per the block diagram (figure 4.4-3), if we follow the clock source
for SYS it traces back to 24MHz Oscillator. Let me know how you want
me to describe this please.

> > +
> > +  resets:
> > +    items:
> > +      - description: SYS_0_PRESETN reset signal
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    extal_clk: extal-clk {
> > +        compatible =3D "fixed-clock";
> > +        #clock-cells =3D <0>;
> > +        clock-frequency =3D <24000000>;
> > +    };
> > +
> > +    sys: system-controller@10430000 {
> > +        compatible =3D "renesas,r9a09g057-sys";
> > +        reg =3D <0x10430000 0x10000>;
> > +        clocks =3D <&extal_clk>;
>
> clocks =3D <&cpg 1>;
>
> (I guess it will be 1 ;-)
>
Yep indeed ;)

Cheers,
Prabhakar

> > +        resets =3D <&cpg 1>;
> > +    };
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m6=
8k.org
>
> In personal conversations with technical people, I call myself a hacker. =
But
> when I'm talking to journalists I just say "programmer" or something like=
 that.
>                                 -- Linus Torvalds