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[209.85.219.173]) by smtp.gmail.com with ESMTPSA id kf17-20020a05622a2a9100b0042c1ce79b4bsm2550581qtb.50.2024.02.26.07.15.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Feb 2024 07:15:08 -0800 (PST) Received: by mail-yb1-f173.google.com with SMTP id 3f1490d57ef6-dc6d8bd618eso3183296276.3; Mon, 26 Feb 2024 07:15:08 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCX1sQNhfz+82LjiYsADSNGz9fozJoDVYDCvFX1vTRBogiX66JzUXPgzrSU9QirWGrdLkLaYstYwFlHSrMOFIqNFdQwoLmd/n+S1fRkH72oJ1TWcNL0IjGWn9L3kUzx9MhZT7B/Pzj8MLrLBvg1SAdN/mVGWw+XGwqAg+Jsug2TLnrA2OW8ZI6TT4NYf X-Received: by 2002:a25:ae99:0:b0:dcc:4cdc:e98f with SMTP id b25-20020a25ae99000000b00dcc4cdce98fmr4795296ybj.34.1708960507928; Mon, 26 Feb 2024 07:15:07 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240219160912.1206647-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240219160912.1206647-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Mon, 26 Feb 2024 16:14:56 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller To: "Lad, Prabhakar" Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Prabhakar, On Mon, Feb 26, 2024 at 3:01=E2=80=AFPM Lad, Prabhakar wrote: > On Mon, Feb 26, 2024 at 1:41=E2=80=AFPM Geert Uytterhoeven wrote: > > On Mon, Feb 19, 2024 at 5:10=E2=80=AFPM Prabhakar wrote: > > > From: Lad Prabhakar > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057= -sys.yaml > > > + clocks: > > > + items: > > > + - description: Clock from external oscillator > > > > Isn't this SYS_0_PCLK inside the CPG? > > > As per the block diagram (figure 4.4-3), if we follow the clock source > for SYS it traces back to 24MHz Oscillator. Let me know how you want > me to describe this please. Yes, that is the diagram I was looking at. MAIN OSC 24 MHz -> MAINCLK -> SYS_0_PCLK. MAIN OSC 24 MHz is a clock input to the CPG. MAINCLK is a CPG internal core clock. SYS_0_PCLK is a CPG clock output, serving as the SYS module clock. I think the standard "maxItems: 1" would be fine, and no description is needed. > > > + > > > + resets: > > > + items: > > > + - description: SYS_0_PRESETN reset signal Same here. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds