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Mon, 26 Feb 2024 07:30:20 -0800 (PST) Date: Mon, 26 Feb 2024 21:00:14 +0530 From: Manivannan Sadhasivam To: Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, Siddharth Vadapalli Subject: Re: [PATCH v3 2/5] PCI: dwc: Skip finding eDMA channels count if glue drivers have passed them Message-ID: <20240226153014.GG8422@thinkpad> References: <20240226-dw-hdma-v3-0-cfcb8171fc24@linaro.org> <20240226-dw-hdma-v3-2-cfcb8171fc24@linaro.org> <5gzkxdpx6u3jhw5twbncjhtozgekmlzxrpj3m6is3ijadm2svb@f6ng4owyakup> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <5gzkxdpx6u3jhw5twbncjhtozgekmlzxrpj3m6is3ijadm2svb@f6ng4owyakup> On Mon, Feb 26, 2024 at 03:53:20PM +0300, Serge Semin wrote: > On Mon, Feb 26, 2024 at 05:07:27PM +0530, Manivannan Sadhasivam wrote: > > In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way > > the drivers can auto detect the number of read/write channels as like its > > predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA > > have to pass the channels count during probe. > > > > To accommodate that, let's skip finding the channels if the channels count > > were already passed by glue drivers. If the channels count passed were > > wrong in any form, then the existing sanity check will catch it. > > > > Suggested-by: Serge Semin > > Reviewed-by: Siddharth Vadapalli > > Signed-off-by: Manivannan Sadhasivam > > --- > > drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++------- > > 1 file changed, 9 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index 193fcd86cf93..ce273c3c5421 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -927,13 +927,15 @@ static int dw_pcie_edma_find_channels(struct dw_pcie *pci) > > { > > u32 val; > > > > - if (pci->edma.mf == EDMA_MF_EDMA_LEGACY) > > - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > > - else > > - val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); > > - > > - pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); > > - pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); > > > + if (!pci->edma.ll_wr_cnt || !pci->edma.ll_rd_cnt) { > > Are you sure that the partly initialized case should be considered as > a request for the auto-detection? IMO &&-ing here and letting the > sanity check to fail further would be more correct since thus the > developer would know about improper initialized data. > We already have the check below. So the partly initialized case will fail anyway. - Mani > -Serge(y) > > > + if (pci->edma.mf == EDMA_MF_EDMA_LEGACY) > > + val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); > > + else > > + val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); > > + > > + pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); > > + pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); > > + } > > > > /* Sanity check the channels count if the mapping was incorrect */ > > if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || > > > > -- > > 2.25.1 > > -- மணிவண்ணன் சதாசிவம்