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AJvYcCVSMbFEaLjwe8jrZXBJXTQbQ9FEWuD2jLhAYv0Lig4oAMCCeN9pVi2pfE4p5Ubef65Mr3Ft0Bd5Vifrkr3jrT6s7RnILNs0TN3oUle1kD2dcjRXlMeGqWltGBmQPyqw4zeTOO+lqvoxIF8jrjgMXnGNK1el9XG+v+LyOfzQ/TJ73lNQBwBy7ZjbzbJf X-Gm-Message-State: AOJu0YzRs3o47w2pRHSvpg2H7jFd7wTAOuwD2pzdz6UheKovrXpsaYOQ EuuTH1LDDUtA/xuTa721VJML1dYaiU0+5zwS3jeTMVfH0SGD2s+p1KxumqoC+OX21yRgy4S5tDR cWbZQW9hYKGL9qYGAl7xVtEHOhgk= X-Received: by 2002:a1f:c642:0:b0:4cb:2662:3651 with SMTP id w63-20020a1fc642000000b004cb26623651mr3650234vkf.6.1708963303632; Mon, 26 Feb 2024 08:01:43 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240219160912.1206647-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240219160912.1206647-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Mon, 26 Feb 2024 16:00:53 +0000 Message-ID: Subject: Re: [PATCH 2/4] dt-bindings: arm: renesas: Document Renesas RZ/V2H{P} System Controller To: Geert Uytterhoeven Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Geert, On Mon, Feb 26, 2024 at 3:15=E2=80=AFPM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Mon, Feb 26, 2024 at 3:01=E2=80=AFPM Lad, Prabhakar > wrote: > > On Mon, Feb 26, 2024 at 1:41=E2=80=AFPM Geert Uytterhoeven wrote: > > > On Mon, Feb 19, 2024 at 5:10=E2=80=AFPM Prabhakar wrote: > > > > From: Lad Prabhakar > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g0= 57-sys.yaml > > > > + clocks: > > > > + items: > > > > + - description: Clock from external oscillator > > > > > > Isn't this SYS_0_PCLK inside the CPG? > > > > > As per the block diagram (figure 4.4-3), if we follow the clock source > > for SYS it traces back to 24MHz Oscillator. Let me know how you want > > me to describe this please. > > Yes, that is the diagram I was looking at. > MAIN OSC 24 MHz -> MAINCLK -> SYS_0_PCLK. > > MAIN OSC 24 MHz is a clock input to the CPG. > MAINCLK is a CPG internal core clock. > SYS_0_PCLK is a CPG clock output, serving as the SYS module clock. > Agreed. > I think the standard "maxItems: 1" would be fine, and no description > is needed. > OK, makes sense. > > > > + > > > > + resets: > > > > + items: > > > > + - description: SYS_0_PRESETN reset signal > > Same here. > Ok. Cheers, Prabhakar