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b=r1oJn0+a119NgRnly85JWrCdEpRX8ETVz5ddFtEgIc9MXs2M+QXhcz3JudJM+7BNCjqKw9WpNkBD39A2KMpiTALDWzOiHeMGDqnQqDUksTHGY6sU1qcSaaP11GMu1miIEfgGLoSxITaPKsE4ouBQatNSnNxcDO1flChq/Qe7fGY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from BL1PR12MB5946.namprd12.prod.outlook.com (2603:10b6:208:399::8) by PH0PR12MB7837.namprd12.prod.outlook.com (2603:10b6:510:282::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.34; Tue, 27 Feb 2024 05:04:41 +0000 Received: from BL1PR12MB5946.namprd12.prod.outlook.com ([fe80::b440:9a95:dbfa:ae67]) by BL1PR12MB5946.namprd12.prod.outlook.com ([fe80::b440:9a95:dbfa:ae67%5]) with mapi id 15.20.7316.034; Tue, 27 Feb 2024 05:04:40 +0000 Message-ID: <9a314461-3097-41a6-a264-1b109f30d3ec@amd.com> Date: Tue, 27 Feb 2024 10:34:28 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next v2 3/4] net: macb: Enable queue disable and WOL Content-Language: en-US To: Andrew Lunn Cc: nicolas.ferre@microchip.com, claudiu.beznea@tuxon.dev, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux@armlinux.org.uk, vadim.fedorenko@linux.dev, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, git@amd.com References: <20240222153848.2374782-1-vineeth.karumanchi@amd.com> <20240222153848.2374782-4-vineeth.karumanchi@amd.com> <024fd8e1-8d1c-4073-99ff-ae8c5d123baa@lunn.ch> <78730bb7-4588-4038-9336-eec6e2635a75@amd.com> <8c0efb9a-d92c-4b9b-be75-498d460f67bd@lunn.ch> From: "Karumanchi, Vineeth" In-Reply-To: <8c0efb9a-d92c-4b9b-be75-498d460f67bd@lunn.ch> Content-Type: text/plain; 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All Cadence GEM IP versions have the >> capability, but specific vendors might enable or disable it as per their >> requirements. > > Do you mean it is an option to synthesizer it or not? So although the > basic IP licensed from Cadence has it, a silicon vendor could remove > it? > Regarding that, we are unsure. However, based on observation from all previous cadence IP's in AMD Soc's, this feature was available. >> WOL was previously enabled via the device-tree attribute. Some users might >> not leverage it. > > This is not typical. If the hardware supports it, we let the end user > decided if they want to use it or not. > > So if all silicon should have it, enable it everywhere. If there is an > option to save some gates and leave it out of the silicon, then we do > need some per device knowledge, or a register which tells us what the > synthesis options where. > I have looked into all config_debug* registers of multiple versions available with us and there is no mention of WOL. I think we can add MACB_WOL_CAPS to default_config and advertise in ethtool by default. Please let me know your suggestions/thoughts. -- ???? vineeth