Received-SPF: pass (google.com: domain of linux-kernel+bounces-83351-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
Precedence: bulk
MIME-Version: 1.0
References: <20240226234532.80114-1-aford173@gmail.com> <20240226234532.80114-6-aford173@gmail.com>
 <20240227083301.4saxxuv4n6aoqnl6@pengutronix.de>
In-Reply-To: <20240227083301.4saxxuv4n6aoqnl6@pengutronix.de>
From: Adam Ford <aford173@gmail.com>
Date: Tue, 27 Feb 2024 07:51:58 -0600
Message-ID: <CAHCN7xKnEvrfYMZau95e7aknTkdqrQLfgWZTfb6mS3Yt5BT6+Q@mail.gmail.com>
Subject: Re: [PATCH V6 5/6] arm64: dts: imx8mp: add HDMI display pipeline
To: Marco Felsch <m.felsch@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, 
	Marek Vasut <marex@denx.de>, Kishon Vijay Abraham I <kishon@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Fabio Estevam <festevam@gmail.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, 
	Will Deacon <will@kernel.org>, Rob Herring <robh@kernel.org>, imx@lists.linux.dev, 
	Sascha Hauer <s.hauer@pengutronix.de>, aford@beaconembedded.com, 
	linux-kernel@vger.kernel.org, Vinod Koul <vkoul@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
	Catalin Marinas <catalin.marinas@arm.com>, Shawn Guo <shawnguo@kernel.org>, 
	Luca Ceresoli <luca.ceresoli@bootlin.com>, devicetree@vger.kernel.org, 
	Lucas Stach <l.stach@pengutronix.de>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Tue, Feb 27, 2024 at 2:33=E2=80=AFAM Marco Felsch <m.felsch@pengutronix.=
de> wrote:
>
> Hi Adam,
>
> thanks a lot for pushing this topic.
>
> On 24-02-26, Adam Ford wrote:
> > From: Lucas Stach <l.stach@pengutronix.de>
> >
> > This adds the DT nodes for all the peripherals that make up the
> > HDMI display pipeline.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> > ---
> > V6:  Make LCDIF3 disabled by default
> >
> > V5:  No change
> >
> > V3:  Re-ordered the HDMI parts to properly come after irqstree_hdmi
> >      inside AIPS4.  Change size of LCDIF3 and PVI to match TRM sizes
> >      of 4KB.
> >
> > V2:  I took this from Lucas' original submission with the following:
> >      Removed extra clock from HDMI-TX since it is now part of the
> >      power domain
> >      Added interrupt-parent to PVI
> >      Changed the name of the HDMI tranmitter to fsl,imx8mp-hdmi-tx
> >      Added ports to HDMI-tx
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 95 +++++++++++++++++++++++
> >  1 file changed, 95 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boo=
t/dts/freescale/imx8mp.dtsi
> > index 18bfa7d9aa7f..637b0265b0f1 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -1940,6 +1940,101 @@ irqsteer_hdmi: interrupt-controller@32fc2000 {
> >                               clock-names =3D "ipg";
> >                               power-domains =3D <&hdmi_blk_ctrl IMX8MP_=
HDMIBLK_PD_IRQSTEER>;
> >                       };
> > +
> > +                     hdmi_pvi: display-bridge@32fc4000 {
> > +                             compatible =3D "fsl,imx8mp-hdmi-pvi";
> > +                             reg =3D <0x32fc4000 0x1000>;
> > +                             interrupt-parent =3D <&irqsteer_hdmi>;
> > +                             interrupts =3D <12>;
> > +                             power-domains =3D <&hdmi_blk_ctrl IMX8MP_=
HDMIBLK_PD_PVI>;
>
> this node should be 'status =3D "disabled";' as reported by Luca else thi=
s
> node will EPROBE_DEFER. With that beeing fixed you can add my:

sorry I missed that one...and I though I was done...sigh.  I hope it's
not too late to get this into the next release.
>
> Tested-by: Marco Felsch <m.felsch@pengutronix.de>
>

I'll push a V7 tonight and add your tested-by.  Thanks for testing.

adam

> Regards,
>   Marco
>
> > +
> > +                             ports {
> > +                                     #address-cells =3D <1>;
> > +                                     #size-cells =3D <0>;
> > +
> > +                                     port@0 {
> > +                                             reg =3D <0>;
> > +                                             pvi_from_lcdif3: endpoint=
 {
> > +                                                     remote-endpoint =
=3D <&lcdif3_to_pvi>;
> > +                                             };
> > +                                     };
> > +
> > +                                     port@1 {
> > +                                             reg =3D <1>;
> > +                                             pvi_to_hdmi_tx: endpoint =
{
> > +                                                     remote-endpoint =
=3D <&hdmi_tx_from_pvi>;
> > +                                             };
> > +                                     };
> > +                             };
> > +                     };
> > +
> > +                     lcdif3: display-controller@32fc6000 {
> > +                             compatible =3D "fsl,imx8mp-lcdif";
> > +                             reg =3D <0x32fc6000 0x1000>;
> > +                             interrupt-parent =3D <&irqsteer_hdmi>;
> > +                             interrupts =3D <8>;
> > +                             clocks =3D <&hdmi_tx_phy>,
> > +                                      <&clk IMX8MP_CLK_HDMI_APB>,
> > +                                      <&clk IMX8MP_CLK_HDMI_ROOT>;
> > +                             clock-names =3D "pix", "axi", "disp_axi";
> > +                             power-domains =3D <&hdmi_blk_ctrl IMX8MP_=
HDMIBLK_PD_LCDIF>;
> > +                             status =3D "disabled";
> > +
> > +                             port {
> > +                                     lcdif3_to_pvi: endpoint {
> > +                                             remote-endpoint =3D <&pvi=
_from_lcdif3>;
> > +                                     };
> > +                             };
> > +                     };
> > +
> > +                     hdmi_tx: hdmi@32fd8000 {
> > +                             compatible =3D "fsl,imx8mp-hdmi-tx";
> > +                             reg =3D <0x32fd8000 0x7eff>;
> > +                             interrupt-parent =3D <&irqsteer_hdmi>;
> > +                             interrupts =3D <0>;
> > +                             clocks =3D <&clk IMX8MP_CLK_HDMI_APB>,
> > +                                      <&clk IMX8MP_CLK_HDMI_REF_266M>,
> > +                                      <&clk IMX8MP_CLK_32K>,
> > +                                      <&hdmi_tx_phy>;
> > +                             clock-names =3D "iahb", "isfr", "cec", "p=
ix";
> > +                             assigned-clocks =3D <&clk IMX8MP_CLK_HDMI=
_REF_266M>;
> > +                             assigned-clock-parents =3D <&clk IMX8MP_S=
YS_PLL1_266M>;
> > +                             power-domains =3D <&hdmi_blk_ctrl IMX8MP_=
HDMIBLK_PD_HDMI_TX>;
> > +                             reg-io-width =3D <1>;
> > +                             status =3D "disabled";
> > +
> > +                             ports {
> > +                                     #address-cells =3D <1>;
> > +                                     #size-cells =3D <0>;
> > +
> > +                                     port@0 {
> > +                                             reg =3D <0>;
> > +
> > +                                             hdmi_tx_from_pvi: endpoin=
t {
> > +                                                     remote-endpoint =
=3D <&pvi_to_hdmi_tx>;
> > +                                             };
> > +                                     };
> > +
> > +                                     port@1 {
> > +                                             reg =3D <1>;
> > +                                             /* Point endpoint to the =
HDMI connector */
> > +                                     };
> > +                             };
> > +                     };
> > +
> > +                     hdmi_tx_phy: phy@32fdff00 {
> > +                             compatible =3D "fsl,imx8mp-hdmi-phy";
> > +                             reg =3D <0x32fdff00 0x100>;
> > +                             clocks =3D <&clk IMX8MP_CLK_HDMI_APB>,
> > +                                      <&clk IMX8MP_CLK_HDMI_24M>;
> > +                             clock-names =3D "apb", "ref";
> > +                             assigned-clocks =3D <&clk IMX8MP_CLK_HDMI=
_24M>;
> > +                             assigned-clock-parents =3D <&clk IMX8MP_C=
LK_24M>;
> > +                             power-domains =3D <&hdmi_blk_ctrl IMX8MP_=
HDMIBLK_PD_HDMI_TX_PHY>;
> > +                             #clock-cells =3D <0>;
> > +                             #phy-cells =3D <0>;
> > +                             status =3D "disabled";
> > +                     };
> >               };
> >
> >               pcie: pcie@33800000 {
> > --
> > 2.43.0
> >
> >
> >