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From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: =?utf-8?Q?Rafa=C5=82_Mi=C5=82ecki?= <zajec5@gmail.com>, Andrew Lunn
 <andrew@lunn.ch>,
 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Rob Herring
 <robh+dt@kernel.org>, Krzysztof Kozlowski
 <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, =?utf-8?Q?Rafa=C5=82_Mi=C5=82ecki?=
 <rafal@milecki.pl>
Subject: Re: [PATCH] arm64: dts: marvell: reorder crypto interrupts on
 Armada SoCs
In-Reply-To: <20240123122258.24218-1-zajec5@gmail.com>
References: <20240123122258.24218-1-zajec5@gmail.com>
Date: Tue, 27 Feb 2024 17:38:49 +0100
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Hi Rafa=C5=82 Mi=C5=82ecki,

> From: Rafa=C5=82 Mi=C5=82ecki <rafal@milecki.pl>
>
> Match order specified in binding documentation. It says "mem" should be
> the last interrupt.
>
> This fixes:
> arch/arm64/boot/dts/marvell/armada-3720-db.dtb: crypto@90000: interrupt-n=
ames:0: 'ring0' was expected
>         from schema $id: http://devicetree.org/schemas/crypto/inside-secu=
re,safexcel.yaml#
> arch/arm64/boot/dts/marvell/armada-3720-db.dtb: crypto@90000: interrupt-n=
ames:1: 'ring1' was expected
>         from schema $id: http://devicetree.org/schemas/crypto/inside-secu=
re,safexcel.yaml#
> arch/arm64/boot/dts/marvell/armada-3720-db.dtb: crypto@90000: interrupt-n=
ames:2: 'ring2' was expected
>         from schema $id: http://devicetree.org/schemas/crypto/inside-secu=
re,safexcel.yaml#
> arch/arm64/boot/dts/marvell/armada-3720-db.dtb: crypto@90000: interrupt-n=
ames:3: 'ring3' was expected
>         from schema $id: http://devicetree.org/schemas/crypto/inside-secu=
re,safexcel.yaml#
> arch/arm64/boot/dts/marvell/armada-3720-db.dtb: crypto@90000: interrupt-n=
ames:4: 'eip' was expected
>         from schema $id: http://devicetree.org/schemas/crypto/inside-secu=
re,safexcel.yaml#
> arch/arm64/boot/dts/marvell/armada-3720-db.dtb: crypto@90000: interrupt-n=
ames:5: 'mem' was expected
>         from schema $id: http://devicetree.org/schemas/crypto/inside-secu=
re,safexcel.yaml#
>
> Signed-off-by: Rafa=C5=82 Mi=C5=82ecki <rafal@milecki.pl>

Applied on mvebu/dt64

Thanks,

Gregory

> ---
>  arch/arm64/boot/dts/marvell/armada-37xx.dtsi  | 10 +++++-----
>  arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 +++++-----
>  2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/bo=
ot/dts/marvell/armada-37xx.dtsi
> index e300145ad1a6..1cc3fa1c354d 100644
> --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> @@ -431,14 +431,14 @@ xor11 {
>  			crypto: crypto@90000 {
>  				compatible =3D "inside-secure,safexcel-eip97ies";
>  				reg =3D <0x90000 0x20000>;
> -				interrupts =3D <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> -					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> +				interrupts =3D <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>  					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>  					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
>  					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> -					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> -				interrupt-names =3D "mem", "ring0", "ring1",
> -						  "ring2", "ring3", "eip";
> +					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names =3D "ring0", "ring1", "ring2",
> +						  "ring3", "eip", "mem";
>  				clocks =3D <&nb_periph_clk 15>;
>  			};
>=20=20
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/b=
oot/dts/marvell/armada-cp11x.dtsi
> index 4ec1aae0a3a9..7e595ac80043 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
> @@ -511,14 +511,14 @@ CP11X_LABEL(sdhci0): mmc@780000 {
>  		CP11X_LABEL(crypto): crypto@800000 {
>  			compatible =3D "inside-secure,safexcel-eip197b";
>  			reg =3D <0x800000 0x200000>;
> -			interrupts =3D <87 IRQ_TYPE_LEVEL_HIGH>,
> -				<88 IRQ_TYPE_LEVEL_HIGH>,
> +			interrupts =3D <88 IRQ_TYPE_LEVEL_HIGH>,
>  				<89 IRQ_TYPE_LEVEL_HIGH>,
>  				<90 IRQ_TYPE_LEVEL_HIGH>,
>  				<91 IRQ_TYPE_LEVEL_HIGH>,
> -				<92 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names =3D "mem", "ring0", "ring1",
> -				"ring2", "ring3", "eip";
> +				<92 IRQ_TYPE_LEVEL_HIGH>,
> +				<87 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names =3D "ring0", "ring1", "ring2", "ring3",
> +					  "eip", "mem";
>  			clock-names =3D "core", "reg";
>  			clocks =3D <&CP11X_LABEL(clk) 1 26>,
>  				 <&CP11X_LABEL(clk) 1 17>;
> --=20
> 2.35.3
>

--=20
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com