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Tue, 27 Feb 2024 18:44:17 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4474F2ADF56; Tue, 27 Feb 2024 18:43:52 +0100 (CET) Received: from [10.252.26.109] (10.252.26.109) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 27 Feb 2024 18:43:49 +0100 Message-ID: <09262390-388f-402f-99e6-ea6229107119@foss.st.com> Date: Tue, 27 Feb 2024 18:43:49 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 10/10] counter: stm32-timer-cnt: add support for capture events Content-Language: en-US To: William Breathitt Gray CC: , , , , , References: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> <20231220145726.640627-11-fabrice.gasnier@foss.st.com> From: Fabrice Gasnier In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_05,2024-02-27_01,2023-05-22_02 On 1/8/24 23:07, William Breathitt Gray wrote: > On Wed, Dec 20, 2023 at 03:57:26PM +0100, Fabrice Gasnier wrote: >> + /* >> + * configure channel in input capture mode, map channel 1 on TI1, channel2 on TI2... >> + * Select both edges / non-inverted to trigger a capture. >> + */ > > I suggest defining a new local variable 'cc' to point to stm32_cc[ch]. I > think that's make the code look nicer here to avoid all the array index > syntax every time you access stm32_cc[ch]. Hi William, Thanks for suggesting. Done. > >> + if (enable) { >> + /* first clear possibly latched capture flag upon enabling */ >> + regmap_read(priv->regmap, TIM_CCER, &ccer); >> + if (!(ccer & stm32_cc[ch].ccer_bits)) { > > Try regmap_test_bits() here instead of using regmap_read(). Done, > >> + sr = ~TIM_SR_CC_IF(ch); >> + regmap_write(priv->regmap, TIM_SR, sr); > > Eliminate 'sr' by regmap_write(priv->regmap, TIM_SR, ~TIM_SR_CC_IF(ch)). > >> @@ -366,6 +460,12 @@ static int stm32_count_events_configure(struct counter_device *counter) >> regmap_write(priv->regmap, TIM_SR, (u32)~TIM_SR_UIF); >> dier |= TIM_DIER_UIE; >> break; >> + case COUNTER_EVENT_CAPTURE: >> + ret = stm32_count_capture_configure(counter, event_node->channel, true); >> + if (ret) >> + return ret; >> + dier |= TIM_DIER_CC_IE(event_node->channel); > > Ah, now I understand why the previous patch OR'd TIM_DIER_UIE to dier. > Apologies for the noise. > >> @@ -374,6 +474,15 @@ static int stm32_count_events_configure(struct counter_device *counter) >> >> regmap_write(priv->regmap, TIM_DIER, dier); >> >> + /* check for disabled capture events */ >> + for (i = 0 ; i < priv->nchannels; i++) { >> + if (!(dier & TIM_DIER_CC_IE(i))) { >> + ret = stm32_count_capture_configure(counter, i, false); >> + if (ret) >> + return ret; >> + } > > Would for_each_clear_bitrange() in linux/find.h work for this loop? I had a look, but it requires to add some variables, for start and stop bit in the bitmap. For now, I've kept the simple BIT macro and bit ops. > >> @@ -504,7 +620,7 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) >> * Some status bits in SR don't match with the enable bits in DIER. Only take care of >> * the possibly enabled bits in DIER (that matches in between SR and DIER). >> */ >> - dier &= TIM_DIER_UIE; >> + dier &= (TIM_DIER_UIE | TIM_DIER_CC1IE | TIM_DIER_CC2IE | TIM_DIER_CC3IE | TIM_DIER_CC4IE); > > Again, sorry for the noise on the previous patch; this makes sense now. > >> @@ -515,6 +631,15 @@ static irqreturn_t stm32_timer_cnt_isr(int irq, void *ptr) >> clr &= ~TIM_SR_UIF; >> } >> >> + /* Check capture events */ >> + for (i = 0 ; i < priv->nchannels; i++) { >> + if (sr & TIM_SR_CC_IF(i)) { > > Would for_each_set_bitrange() in linux/find.h work for this loop? same. > >> + counter_push_event(counter, COUNTER_EVENT_CAPTURE, i); >> + clr &= ~TIM_SR_CC_IF(i); > > Perhaps u32p_replace_bits(&clr, 0, TIM_SR_CC_IF(i)) is clearer here. I've hit some build issue with TIM_SR_CC_IF(i) macro, e.g.: /include/linux/bitfield.h:165:17: error: call to ‘__bad_mask’ declared with attribute error: bad bitfield mask 165 | __bad_mask(); So I've kept the simple bit operation here. Thanks & Best Regards, Fabrice > >> @@ -627,8 +752,11 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) >> } >> } else { >> for (i = 0; i < priv->nr_irqs; i++) { >> - /* Only take care of update IRQ for overflow events */ >> - if (i != STM32_TIMERS_IRQ_UP) >> + /* >> + * Only take care of update IRQ for overflow events, and cc for >> + * capture events. >> + */ >> + if (i != STM32_TIMERS_IRQ_UP && i != STM32_TIMERS_IRQ_CC) >> continue; > > Okay, I see now why you have this check. This should be fine as it'll > makes adding support in the future for the other IRQs a less invasive > change. > > William Breathitt Gray