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Wed, 28 Feb 2024 01:17:19 GMT Received: from [10.71.111.211] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 27 Feb 2024 17:17:16 -0800 Message-ID: <65e9ef21-3406-4632-a607-2c4e9d587131@quicinc.com> Date: Tue, 27 Feb 2024 17:17:16 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/5] arm64: dts: qcom: sm8550: Add mapping to llcc Broadcast_AND region Content-Language: en-US To: Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , References: <4e5129de-ce1d-448c-9264-b7470c3feb49@linaro.org> From: Unnathi Chalicheemala In-Reply-To: <4e5129de-ce1d-448c-9264-b7470c3feb49@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: M6c5ZJaqYN770YvSyJn-XDe31zd8gq9u X-Proofpoint-GUID: M6c5ZJaqYN770YvSyJn-XDe31zd8gq9u X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-27_11,2024-02-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 mlxlogscore=834 clxscore=1015 suspectscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402280008 On 2/27/2024 7:49 AM, Krzysztof Kozlowski wrote: > On 23/02/2024 00:07, Unnathi Chalicheemala wrote: >> Mapping Broadcast_AND region for LLCC in SM8550. > > I don't understand this sentence and I still do not know why. > The check of whether status bit is 1 in the driver is being done with the wrong register all along (sm8450 onwards). So I am adding the base address of the right register region in the DeviceTree files. I can add this explanation to the commit message of these patches if you think that would help. > Best regards, > Krzysztof >