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From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Date: Wed, 28 Feb 2024 13:43:05 +0800
Subject: [PATCH v2 1/2] dt-bindindgs: clock: support NXP i.MX95 BLK CTL
 module
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To: Abel Vesa <abelvesa@kernel.org>, 
 Michael Turquette <mturquette@baylibre.com>, 
 Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
 Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, 
 Sascha Hauer <s.hauer@pengutronix.de>, 
 Pengutronix Kernel Team <kernel@pengutronix.de>, 
 Fabio Estevam <festevam@gmail.com>
Cc: linux-clk@vger.kernel.org, imx@lists.linux.dev, 
 devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, 
 linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
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	=?utf-8?B?Zy9ybzNpbjNVVlpIMjNJdVNIaFZnb25vWEZCQnVqbDVZR3VVTEk3VEhNejBa?=
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 =?utf-8?B?UzJ6TElsU1h2SG42NjJuamV4VTc0Y2FkZjZXUzlzSUg2OUw1SFdwYnBCb05Y?=
 =?utf-8?B?b3JoWktVcEpSdFhISGNyMzJSbmovWFNwTUdhWFU4dm1Oeis2U0g0YnBBL3gz?=
 =?utf-8?B?NjZveG1HSWpIUjJMd2dvS3ZZYTZqcThRWEFGbFpMSTBieTVOYm1DWkRpREZn?=
 =?utf-8?B?dytYR2xGVExvQmJKQkdkZGZBaHZzQ1lBZENyUVBRdmNCWnFkUFlkTjhjK25F?=
 =?utf-8?B?Z2tmWlcyVnB0MmV4NlhOcEJuTkw4cnJUamdWRHFVZFZGcEgycW13NmdhS2VO?=
 =?utf-8?B?eWl6TnpUWVhYa1lGQjRkTW0xUUU4Ti9Lc2FMbjIwbkxkZ1QzdTFONkxjVXlV?=
 =?utf-8?B?UjVWc1RvTmw1TzBJZ1pHdEV3KzdmZHhZVDZZMkhXU2hzNlA0OC9ISXM3ZGxs?=
 =?utf-8?B?VjNyV3Mvb0MrMUc4eUhYeERGUWYyVlhKQWlYbWdMVFc0aFA1MFdEZEtWdWsr?=
 =?utf-8?B?TEg4d2pjcDZCbnFTU013MHYvZ2d2emM3Nm5sVTE5WURXL1Myb21BQ0VPUFRp?=
 =?utf-8?B?b0R1Z0JWcjY0ZFp6QzJRTFpOUFFIb2R2c2FuclZOQ2RPN1dkekd6UUw2TTk4?=
 =?utf-8?B?dVg4azZYbXc4VlZObWpDVmNUcWtvQkxvdzR0Q2loM3JZVGk5SzRsUGJMdWpP?=
 =?utf-8?B?bWVzQTdVRGFad1Zvbk1PejJCaDlZTmJreTM0N3JTWDdrM01xb01mREV2czNM?=
 =?utf-8?B?OW0xSUlFaC96aDM3aHZ6Q0wvNVZ0aVY3eFhDTkNZdTVPdWp5b0Njc1E0a2tt?=
 =?utf-8?B?cm1LSXBtbStwb1pyaHM1ZXZGWkRzWjR5MkFGeHVRb1FpMXFvdEs1b093anhJ?=
 =?utf-8?B?WjExTTh6Qk53WXVScnhrQUlHZ0RCWkhCYTZoMWxuYmNmeUpHNUlSREVVSER4?=
 =?utf-8?B?ZWxGT0x0b3lKcmIzdjExN2NYNU8zbEJkb3FNMGJ3NzJDOUxHYnhZWGRUU21T?=
 =?utf-8?B?RDZHM0lJcHB0bHdpRzkycWhJcTJ5VkkyYlF1TG9nMWRqTi9YTlZhSU5OZEhj?=
 =?utf-8?B?Y0NHNzMrVElTZTFrMURaeTkrZ1RmR0djQVY1em5YVWNqelB3d1BvMjEzbGl2?=
 =?utf-8?B?Qk5vYjV2dThpTitGcUUzNytqa1NUaUVnQjVOaHV2ZjRJSzBYNzkzUENTRHJl?=
 =?utf-8?B?dEJDNGNJUmtkb0RoNjFFSE9Ga2U3MDljby9TZEYvOU03MmpwOXhWNVEyNWZl?=
 =?utf-8?B?QkhraDVuTVV4NkJrRHV0czhJcklHT1VudGI1ZnJ0U3FGQzhvWGp5ckE4UXBP?=
 =?utf-8?B?Q09FYWNzZkp6L3phZ0IvS2loRXpES0pkUmVROXk3Vmgxc21UVnUrWDQ0anZ2?=
 =?utf-8?B?TE5QMWl3d0FndHhhZXVmT25UVmpiRm0zUjhJcXc2bVBNSUNlbmdWODVWMmFw?=
 =?utf-8?B?ODBzRVRkUEtJd0I5dGZ1S2tRV3YxcmRLZHBiMHhJMGd5amE2SktFTUs1Rmcr?=
 =?utf-8?B?ODN2K29lelVvSkZHVFI0YXYvU3NNV3RqdnFPZElBbVNFN3VSL1hvS0lFWWN2?=
 =?utf-8?B?YkFTYTMxWVFvQ3YvdE9kQXNYOE55bWxyUGVGbG1JR2ZUTnFVTzI3MStUTGZZ?=
 =?utf-8?B?SElBcHF4L1hONVVTWW9sSE5BUDdJcXVrUnNZN01FTWQveW1YWXdhWVdZSFFm?=
 =?utf-8?B?RkZQMWl1QUVJVXRPRFA5TGdaSldDMEJNYlZzY3k5L1ZkeHNWODJ1b1NJeEVN?=
 =?utf-8?B?c3RicEFUM1J0OWtKZVA4azFIMlVJYktYTWVjRTN3VEJkZmV5bi9ibHNRNTg1?=
 =?utf-8?B?MXcrRmpDT0hlcFFvL0pnVmpjYXNLNXhvOWJ0eDFESnl2aU5vMzVzRFdGbVhM?=
 =?utf-8?B?T3hSTTV5Rk9vMHFaR3BrdVlGd0NmWEhOR0d6TmZRV1RwaUdNby9OL3N0cHpz?=
 =?utf-8?B?ZGdHamxWN2dLcHpZcnNoRTZvOXJwL3hDYW9WbUUxa0dPM2hQOEpORVh4NkRj?=
 =?utf-8?B?c2w5OFdRSUNvNFgvTEFiKzFBYk1uY0RSQlBBbkdtdVFHL3Q1aS9peEI3d3hS?=
 =?utf-8?Q?VnxjnbdNlOKAmSDT0V33wt+Ms?=
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From: Peng Fan <peng.fan@nxp.com>

i.MX95 includes BLK CTL module in several MIXes, such as VPU_CSR in
VPUMIX, BLK_CTRL_NETCMIX in NETCMIX, CAMERA_CSR in CAMERAMIX and etc.

The BLK CTL module is used for various settings of a specific MIX, such
as clock, QoS and etc.

This patch is to add some BLK CTL modules that has clock features.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 .../devicetree/bindings/clock/imx95-blk-ctl.yaml   | 61 ++++++++++++++++++++++
 include/dt-bindings/clock/nxp,imx95-clock.h        | 32 ++++++++++++
 2 files changed, 93 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/imx95-blk-ctl.yaml
new file mode 100644
index 000000000000..6d33601034ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx95-blk-ctl.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx95-blk-ctl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX95 Block Control
+
+maintainers:
+  - Peng Fan <peng.fan@nxp.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - nxp,imx95-cameramix-csr
+          - nxp,imx95-display-master-csr
+          - nxp,imx95-dispmix-lvds-csr
+          - nxp,imx95-dispmix-csr
+          - nxp,imx95-netcmix-blk-ctrl
+          - nxp,imx95-vpumix-csr
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      The clock consumer should specify the desired clock by having the clock
+      ID in its "clocks" phandle cell. See
+      include/dt-bindings/clock/nxp,imx95-clock.h
+
+  mux-controller:
+    type: object
+    $ref: /schemas/mux/reg-mux.yaml
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  # Clock Control Module node:
+  - |
+    #include <dt-bindings/clock/nxp,imx95-clock.h>
+
+    syscon@4c410000 {
+      compatible = "fsl,imx95-vpumix-csr", "syscon";
+      reg = <0x4c410000 0x10000>;
+      #clock-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h
new file mode 100644
index 000000000000..09120e098a97
--- /dev/null
+++ b/include/dt-bindings/clock/nxp,imx95-clock.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX95_H
+#define __DT_BINDINGS_CLOCK_IMX95_H
+
+#define IMX95_CLK_DISPMIX_ENG0_SEL		0
+#define IMX95_CLK_DISPMIX_ENG1_SEL		1
+#define IMX95_CLK_DISPMIX_END			2
+
+#define IMX95_CLK_DISPMIX_LVDS_PHY_DIV		0
+#define IMX95_CLK_DISPMIX_LVDS_CH0_GATE		1
+#define IMX95_CLK_DISPMIX_LVDS_CH1_GATE		2
+#define IMX95_CLK_DISPMIX_PIX_DI0_GATE		3
+#define IMX95_CLK_DISPMIX_PIX_DI1_GATE		4
+#define IMX95_CLK_DISPMIX_LVDS_CSR_END		5
+
+#define IMX95_CLK_VPUBLK_WAVE			0
+#define IMX95_CLK_VPUBLK_JPEG_ENC		1
+#define IMX95_CLK_VPUBLK_JPEG_DEC		2
+#define IMX95_CLK_VPUBLK_END			3
+
+#define IMX95_CLK_CAMBLK_CSI2_FOR0		0
+#define IMX95_CLK_CAMBLK_CSI2_FOR1		1
+#define IMX95_CLK_CAMBLK_ISP_AXI		2
+#define IMX95_CLK_CAMBLK_ISP_PIXEL		3
+#define IMX95_CLK_CAMBLK_ISP			4
+#define IMX95_CLK_CAMBLK_END			5
+
+#endif	/* __DT_BINDINGS_CLOCK_IMX95_H */

-- 
2.37.1