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Subject: Re: [PATCH] clk: allow to skip clk_core_req_round_rate_nolock()
From: Stephen Boyd <sboyd@kernel.org>
Cc: kernel@salutedevices.com
To: Jan Dakinevich <jan.dakinevich@salutedevices.com>, Michael Turquette <mturquette@baylibre.com>, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Date: Wed, 28 Feb 2024 18:16:24 -0800
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Quoting Jan Dakinevich (2024-02-23 13:47:35)
>=20
>=20
> On 2/23/24 02:20, Stephen Boyd wrote:
> > Quoting Jan Dakinevich (2024-01-26 12:14:33)
> >> Calling of clk_core_req_round_rate_nolock() can be time-consuming in a
> >> case of deep hierarchy with multiple dividers/parents. But if the clock
> >> already has exactly the same rate as desired, there is no need to
> >> determine how it could be rounded.
> >=20
> > What exactly are you trying to avoid? Is this an optimization or a bug
> > fix? TL;DR: I'm unlikely to apply this patch.
> >=20
>=20
> It is an optimization, not a bug. The problem is that=20
> clk_core_req_round_rate_nolock() is quite expensive, and I faced with=20
> cases, where it takes tens and hundreds milliseconds (depending on SoC).
>=20
> As I see, it is irremovable feature of clk_core_req_round_rate_nolock()=20
> design itself. Lets imagine, we have some clock, and its parent is a=20
> divider. When clk_core_req_round_rate_nolock() is being called the=20
> execution is walked through the following path:
>=20
> clk_core_determine_round_nolock
>   core->ops->determine_rate
>     divider_determine_rate
>      clk_divider_bestdiv
>=20
> Inside clk_divider_bestdiv() for each possible divider=20
> clk_hw_round_rate() is called for parent of the clock, which in turn=20
> calls clk_core_determine_round_nolock().
>=20
> So, each divider and multiplexer in clock path multiplies many times an=20
> amount of iteration required to execute=20
> clk_core_req_round_rate_nolock(). When there are a lot of them the time=20
> consumed by clk_core_req_round_rate_nolock() becomes sufficient.

Do you have a more concrete example? I wonder if perhaps you've split up
the clk hardware into multipliers and dividers, when they really could
all be combined into one clk that does all the math at once without
traversing the tree. But if the problem is really just that the
clk_divider_bestdiv() implementation is slow then that's good to know.

>=20
> > I could see some driver implementing round_rate()/determine_rate() in a
> > way that rounds the rate passed in, so that even if the rate is what the
> > clk is running at _right now_, it still wants to change it to something
> > else, or at least call down into the driver to call the set_rate clk_op.
> > Applying this patch will break that. The contract is that
> > clk_set_rate(rate) =3D=3D clk_set_rate(clk_round_rate(rate)). It doesn't
> > look like anything needs to change.
>=20
> If I am not mistaken, clocks's rate is either equal to its parent rate=20
> or calculated by ->recalc_rate(). I suppose, this callback should return =

> valid rate value that is based on current clock parameters.
>=20
> Now, suppose the clock has rate "rateA" and we called clk_set_rate() to=20
> set "rateA", but clk_core_req_round_rate_nolock() inside clk_set_rate()=20
> rounds it to "rateB". Thus, although the clock is able to run on desired =

> rate (and actually run on it), ->determine_rate() and ->round_rate() are =

> unable to choose clocks's parameters for that value. Is it correct=20
> behavior for clock driver?
>=20

It's not really a question for the clk framework. If the clk driver
wants to round rateA to rateB then it can. It could be that the
recalc_rate() clk_op calculates a slightly different rate than what
round_rate() clk op did, because maybe the driver has frequency tables
and the rate the clk runs at is something like 933333Hz but the driver
just says that's 930000Hz for simplicity. If that happens, recalc_rate()
gives us the "true" rate, while round_rate() gives us the "approximate"
rate. Either way, the set_rate() clk_op knows that 930000Hz means set
some clk rate, even if that doesn't match what recalc_rate() returns
once the rate is changed.

This is very much a real case, because this is essentially how the qcom
clk driver works.