Received: by 2002:ab2:2997:0:b0:1ec:cbc4:63fb with SMTP id n23csp371481lqb; Thu, 29 Feb 2024 03:42:28 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWyfhmceVOnC2x2kVaechzPEbp5tqKEz4KjFVhvkj+ilJsLFFiOmddk6YTKqa43DF76Kt3w0QxGFzF0o8UzCajaZOpab3t9/RPQka4raw== X-Google-Smtp-Source: AGHT+IEtWwYTnYEeoOIMLfE0Ov9rupdSyFQe33DnYewq8PVgHsJoNTYLft0hI3rfgSZXcUE4PU+s X-Received: by 2002:a9d:6484:0:b0:6e4:2fdf:64ac with SMTP id g4-20020a9d6484000000b006e42fdf64acmr1757891otl.16.1709206948506; Thu, 29 Feb 2024 03:42:28 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709206948; cv=pass; d=google.com; s=arc-20160816; b=c+UfuJybfDMc/zxJCuV6QMHNzrBtozomkd8lmvigb4K/kIxdgt+ZpqDQWpLybXiFbg KBSRTqB1tcc9Wb35978XxgfPq3AG/g6rPGXe8gtF9AlBPN+QMqGzE48w08DxCHyicAAv a02TWb0al24kjvoQsDlKppuSOVHpAt3rLx2/kq9LRr8AfGovB5LunkNRgpIMN45PEDzM wiGoLzfPVximcuvjznRhz2lFVtjPQHVcueM0WAgs5Qzv8ReLr6f0iCrmhWNtgNcCoIUw gvKEZfvsHXUjQTJIAS36H9asGMcRM9PO3E7flmtLh//o2AVpinY1lttnyK234eqypWTJ cPUw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=YDRsjjOZHwu4Og/NNIRtmyTJHBezn1V5tRuGYf4kPMk=; fh=aCwmaRkx6C6CiKPbzjlx1NxeLmAOFbuKLHzIFpBJXhk=; b=TbgKuw4trdFVDgf8NtkxmlwUsHnJhnj5rmIMsx5mEkRc4/AbxftHrKXiYnEq7mdwy6 wahQ6QdeA+WKMSiwzxCcU/kdZQO6U8ridFuYC3DmwVVViUQnoko5f6gLdkzFjZhHfEcW BaPDbbjX95s2mgpv02GIF8KUjbk2u6LgyOoAuF8NvvS6eUSVgBzUdbmDmDoI83PudQDK 8XwjioFTyP4V5A1qrSOWpRcw2lAerAFZVgcZs78m7rvkKz0FKaIjNVXf0w/0NN+3GCGS kyxCtva903I3Fkt9eMleAuYe72/IC/yxvIAj/R3rrVQEdsehsikli7qDq61/+yZc6jkn aZgA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=nww28hpV; arc=pass (i=1 spf=pass spfdomain=microchip.com dkim=pass dkdomain=microchip.com dmarc=pass fromdomain=microchip.com); spf=pass (google.com: domain of linux-kernel+bounces-86642-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-86642-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com Return-Path: Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id d7-20020a633607000000b005dbde399b23si1176145pga.901.2024.02.29.03.42.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Feb 2024 03:42:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-86642-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=nww28hpV; arc=pass (i=1 spf=pass spfdomain=microchip.com dkim=pass dkdomain=microchip.com dmarc=pass fromdomain=microchip.com); spf=pass (google.com: domain of linux-kernel+bounces-86642-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-86642-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 07AC2286B8B for ; Thu, 29 Feb 2024 11:42:25 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 165D57A709; Thu, 29 Feb 2024 11:42:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="nww28hpV" Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36EB57C094; Thu, 29 Feb 2024 11:42:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709206939; cv=none; b=JsmCveYi8tIqdZgiPck5Lc3Tf+rgp/JpYkSwQ1ObdaugllLZr5M6SYKnMYb1Qli3PWta0FdvZTM6RXI117tlyM4osyTkxmRywQFvW68CR1r1gmo0loAXcfWnTzsjL+PxR5jAedn+YHLF5YGEEzTpj4qaMkdUBeRECnkCk2yBbkg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709206939; c=relaxed/simple; bh=88/nCfzcv/0mBvz7vctQH4WqIZwLFpdPUBRZoFLWORs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Ax1M/tVsajddnaNLIz4nCw+vBQc/INVUirXz/o94bHEya10JWfVOE3WEsYXZ5FD3F3neiFVmA2RoTEQY4QbbbJYDxkZCrnjoqzAUgVoiT5wxvzJXPEclGmwCgJ3iQdflbbkIWLsDJ9evkk0YTOkolnxOtKgC1lzsrDc5WthcO1w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=nww28hpV; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1709206937; x=1740742937; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=88/nCfzcv/0mBvz7vctQH4WqIZwLFpdPUBRZoFLWORs=; b=nww28hpVyvOqhGMkGarA4erIy5O4P2IWJy/mqZ76VUcpcl/Of81JfMPY rQhhSwuYqUD6PZbCXYWgYG9ej43yLBgc71ljUzYPe7l7GmAB19HUyMi/l EAMsCtN3niEbo6zqzTQeYoY+7Npa6ln1OJfUIiU9H9rM4dGVSAbuksLhv iM0MmWHPTHsnaBWmKIybXmfVf6ysCcsUtvZrkTgJ6xOTQvxv6Fh8L0ZIg tDLQFlFS6fwAYq/sLzAARf7n26JzntHe3IYXTIEnyVA+V45VBdlmz0WaG ncI6Ju+ebE6WOCBLtXJrtx2E1kNQ/RVqdrNIMVUv84Jb3H28Cmt00U5fv Q==; X-CSE-ConnectionGUID: d8+oGP1LQdGqNaTtcEJPXQ== X-CSE-MsgGUID: q8U8MYpsRv2FsgSctH5nmA== X-IronPort-AV: E=Sophos;i="6.06,194,1705388400"; d="scan'208";a="247759793" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 29 Feb 2024 04:42:16 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 29 Feb 2024 04:41:45 -0700 Received: from [127.0.1.1] (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 29 Feb 2024 04:41:42 -0700 From: Balakrishnan Sambath Date: Thu, 29 Feb 2024 17:09:32 +0530 Subject: [PATCH 3/3] dt-bindings: pinctrl: at91-pio4: convert Atmel's PIO4 bindings to json-schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20240229-pio4-pinctrl-yaml-v1-3-c4d8279c083f@microchip.com> References: <20240229-pio4-pinctrl-yaml-v1-0-c4d8279c083f@microchip.com> In-Reply-To: <20240229-pio4-pinctrl-yaml-v1-0-c4d8279c083f@microchip.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Linus Walleij CC: , , , , "Balakrishnan Sambath" X-Mailer: b4 0.13.0 Convert the existing text DT bindings of Atmel's PIO4 pincontroller to yaml based DT schema. Signed-off-by: Balakrishnan Sambath --- .../bindings/pinctrl/atmel,at91-pio4-pinctrl.txt | 98 --------------- .../bindings/pinctrl/atmel,sama5d2-pinctrl.yaml | 140 +++++++++++++++++++++ 2 files changed, 140 insertions(+), 98 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt deleted file mode 100644 index 774c3c269c40..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ /dev/null @@ -1,98 +0,0 @@ -* Atmel PIO4 Controller - -The Atmel PIO4 controller is used to select the function of a pin and to -configure it. - -Required properties: -- compatible: - "atmel,sama5d2-pinctrl" - "microchip,sama7g5-pinctrl" -- reg: base address and length of the PIO controller. -- interrupts: interrupt outputs from the controller, one for each bank. -- interrupt-controller: mark the device node as an interrupt controller. -- #interrupt-cells: should be two. -- gpio-controller: mark the device node as a gpio controller. -- #gpio-cells: should be two. - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -Subnode format -Each node (or subnode) will list the pins it needs and how to configured these -pins. - - node { - pinmux = ; - GENERIC_PINCONFIG; - }; - -Required properties: -- pinmux: integer array. Each integer represents a pin number plus mux and -ioset settings. Use the macros from boot/dts/-pinfunc.h file to get the -right representation of the pin. - -Optional properties: -- GENERIC_PINCONFIG: generic pinconfig options to use: - - bias-disable, bias-pull-down, bias-pull-up, drive-open-drain, - drive-push-pull input-schmitt-enable, input-debounce, output-low, - output-high. - - for microchip,sama7g5-pinctrl only: - - slew-rate: 0 - disabled, 1 - enabled (default) -- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for -high drive. The default value is low drive. - -Example: - -#include - -... -{ - pioA: pinctrl@fc038000 { - compatible = "atmel,sama5d2-pinctrl"; - reg = <0xfc038000 0x600>; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, - <68 IRQ_TYPE_LEVEL_HIGH 7>, - <69 IRQ_TYPE_LEVEL_HIGH 7>, - <70 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - clocks = <&pioA_clk>; - - pinctrl_i2c0_default: i2c0_default { - pinmux = , - ; - bias-disable; - }; - - pinctrl_led_gpio_default: led_gpio_default { - pinmux = , - ; - bias-pull-up; - atmel,drive-strength = ; - }; - - pinctrl_sdmmc1_default: sdmmc1_default { - cmd_data { - pinmux = , - , - , - , - ; - bias-pull-up; - }; - - ck_cd { - pinmux = , - ; - bias-disable; - }; - }; - ... - }; -}; -... diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,sama5d2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/atmel,sama5d2-pinctrl.yaml new file mode 100644 index 000000000000..8a2dee1d6dd3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/atmel,sama5d2-pinctrl.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/atmel,sama5d2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIO4 Controller + +maintainers: + - Balakrishnan Sambath + +description: + The Microchip PIO4 controller is used to select the function of a pin and to + configure it. + + +properties: + compatible: + enum: + - microchip,sama7g5-pinctrl + - atmel,sama5d2-pinctrl + + reg: + minItems: 1 + maxItems: 2 + + interrupts: + description: + Interrupt outputs from the controller, one for each bank. + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + clocks: + maxItems: 1 +if: + properties: + compatible: + contains: + const: microchip,sama7g5-pinctrl +then: + patternProperties: + '^.*([-_]default)?$': + anyOf: + - $ref: "#/$defs/mchp-pio4-pincfg-node-1" + - patternProperties: + '^[a-z_-][a-z_-]*$': + $ref: "#/$defs/mchp-pio4-pincfg-node-1" +else: + patternProperties: + '^.*([-_]default)?$': + anyOf: + - $ref: "#/$defs/mchp-pio4-pincfg-node-2" + - patternProperties: + '^[a-z_-][a-z_-]*$': + $ref: "#/$defs/mchp-pio4-pincfg-node-2" + +$defs: + mchp-pio4-pincfg-node-1: + $ref: pincfg-node.yaml#properties + properties: + pinmux: + $ref: pinmux-node.yaml#/properties/pinmux + atmel,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + required: + - pinmux + + mchp-pio4-pincfg-node-2: + $ref: pincfg-node.yaml#properties + properties: + pinmux: + $ref: pinmux-node.yaml#/properties/pinmux + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + pinctrl@fc038000 { + compatible = "atmel,sama5d2-pinctrl"; + reg = <0xfc038000 0x600>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, + <68 IRQ_TYPE_LEVEL_HIGH 7>, + <69 IRQ_TYPE_LEVEL_HIGH 7>, + <70 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&pioA_clk>; + + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = , + , + , + , + ; + bias-pull-up; + }; + + ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + }; +... -- 2.25.1