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Date: Thu, 29 Feb 2024 15:27:01 +0100
Message-Id: <CZHMSNWMH4KJ.2J6ZMWKMSZYH2@bootlin.com>
From: =?utf-8?q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>
Subject: Re: [PATCH v8 03/10] clk: eyeq5: add platform driver, and init
 routine at of_clk_init()
Cc: "Gregory CLEMENT" <gregory.clement@bootlin.com>, "Michael Turquette"
 <mturquette@baylibre.com>, "Stephen Boyd" <sboyd@kernel.org>, "Rob Herring"
 <robh+dt@kernel.org>, "Krzysztof Kozlowski"
 <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley" <conor+dt@kernel.org>,
 "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>, "Linus Walleij"
 <linus.walleij@linaro.org>, =?utf-8?q?Rafa=C5=82_Mi=C5=82ecki?=
 <rafal@milecki.pl>, "Philipp Zabel" <p.zabel@pengutronix.de>, "Vladimir
 Kondratiev" <vladimir.kondratiev@mobileye.com>,
 <linux-mips@vger.kernel.org>, <linux-clk@vger.kernel.org>,
 <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, "Thomas
 Petazzoni" <thomas.petazzoni@bootlin.com>, "Tawfik Bayouk"
 <tawfik.bayouk@mobileye.com>, <linux-gpio@vger.kernel.org>
To: "Andy Shevchenko" <andriy.shevchenko@intel.com>
References: <20240227-mbly-clk-v8-0-c57fbda7664a@bootlin.com>
 <20240227-mbly-clk-v8-3-c57fbda7664a@bootlin.com>
 <Zd4X3NnBoEl0wu2H@smile.fi.intel.com>
 <CZGSB2O8P572.28HK6WFT43N6S@bootlin.com>
 <ZeBnX2upNRN0xXH4@smile.fi.intel.com>
In-Reply-To: <ZeBnX2upNRN0xXH4@smile.fi.intel.com>

Hello,

On Wed, Feb 28, 2024 at 03:33:29PM +0100, Th=C3=A9o Lebrun wrote:
> On Tue Feb 27, 2024 at 6:11 PM CET, Andy Shevchenko wrote:
> > On Tue, Feb 27, 2024 at 03:55:24PM +0100, Th=C3=A9o Lebrun wrote:

[...]

> > > > +	u32		reg;	/* next 8 bytes are r0 and r1 */
> > >
> > > Not sure this comments gives any clarification to a mere reader of th=
e code.
> > > Perhaps you want to name this as reg64 (at least it will show that yo=
u have
> > > 8 bytes, but I have no clue what is the semantic relationship between=
 r0 and
> > > r1, it's quite cryptic to me). Or maybe it should be reg_0_1?
> >=20
> > Clocks are defined by two 32-bit registers. We only store the first
> > register offset because they always follow each other.
>
> > I like the reg64 name and will remove the comment. This straight forwar=
d
> > code is found in the rest of the code, I don't think it is anything
> > hard to understand (ie does not need a comment):
> >=20
> > 	u32 r0 =3D readl(base_plls + pll->reg);
> > 	u32 r1 =3D readl(base_plls + pll->reg + sizeof(r0));
>
> Btw, why readq()/writeq() (with probably the inclusion of io-64-nonatomic=
-lo-hi.h)
> can be used in this case? It will be much better overall and be aligned w=
ith
> reg64 name.

The doc talks in terms of 32-bit registers. I do not see a reason to
work in 64-bit. If we get a 64-bit value that we need to split we need
to think about the endianness of our platform, which makes things more
complex than just reading both values independently.

> [...]
>
> > > I didn't get. If eq5c_init() was finished successfully, why do you ne=
ed to
> > > seems repeat what it already done? What did I miss?
> >=20
> > The key here is that eq5c_init() iterates on eq5c_early_plls[] while
> > eq5c_probe() iterates on eq5c_plls[]. I've tried to hint at this in the
> > commit message:
> >=20
> > > Two PLLs are required early on and are therefore registered at
> > > of_clk_init(). Those are pll-cpu for the GIC timer and pll-per for th=
e
> > > UARTs.
> >=20
> > Doing everything in eq5c_init() is not clean because we expect all new
> > clock provider drivers to be standard platform drivers. Doing
> > everything from a platform driver probe doesn't work because some
> > clocks are required earlier than platform bus init. We therefore do a
> > mix.
>
> Am I missing something or these two pieces are using the same IO resource=
s?
> This looks like a lot of code duplication without clear benefit. Perhaps
> you can have a helper?

There are two subtle differences that make creating a helper difficult:

 - Logging, pr_*() vs dev_*(). Second option is preferred but only
   available once a device is created.

 - Behavior on error: we stop the world for early clocks but keep going
   for normal clocks.

[...]

> > > > +		eq5c_clk_data->hws[pll->index] =3D hw;
> > > > +		if (IS_ERR(hw))
> > >
> > > > +			dev_err_probe(dev, PTR_ERR(hw), "failed registering %s\n",
> > > > +				      pll->name);
> > >
> > > Missed return statement?
> >=20
> > No, we still try to register all clocks even if one failed. I guess we
> > can call this being optimistic.
>
> But how critical these clocks are? I believe we should panic it we have n=
o
> critical calls be available. Otherwise, why '_err_'? Shouldn't be dev_war=
n()?

Indeed printing should be dev_warn(), I missed that.

Thanks Andy,

--
Th=C3=A9o Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com