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Thu, 29 Feb 2024 22:24:05 GMT Received: from hu-cgoldswo-sd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 29 Feb 2024 14:24:04 -0800 Date: Thu, 29 Feb 2024 14:24:03 -0800 From: Chris Goldsworthy To: Georgi Djakov CC: Krzysztof Kozlowski , Georgi Djakov , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v5 1/7] dt-bindings: iommu: Add Qualcomm TBU bindings Message-ID: <20240229222347.GA918@hu-cgoldswo-sd.qualcomm.com> References: <20240226172218.69486-1-quic_c_gdjako@quicinc.com> <20240226172218.69486-2-quic_c_gdjako@quicinc.com> <70095e04-eaec-4323-b2ac-2d4d366763d5@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <70095e04-eaec-4323-b2ac-2d4d366763d5@kernel.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: OXH1O4Jm_oC6uUujkc43pumk01oZDJUg X-Proofpoint-ORIG-GUID: OXH1O4Jm_oC6uUujkc43pumk01oZDJUg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-29_06,2024-02-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 mlxlogscore=999 impostorscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402290175 On Thu, Feb 29, 2024 at 10:09:34PM +0200, Georgi Djakov wrote: > Hi Krzysztof, > > On 29.02.24 19:53, Krzysztof Kozlowski wrote: > >On 26/02/2024 18:22, Georgi Djakov wrote: > >>+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >>+%YAML 1.2 > >>+--- > >>+$id: http://devicetree.org/schemas/iommu/qcom,tbu.yaml# > >>+$schema: http://devicetree.org/meta-schemas/core.yaml# > >>+ > >>+title: Qualcomm TBU (Translation Buffer Unit) > >>+ > >>+maintainers: > >>+ - Georgi Djakov > >>+ > >>+description: > >>+ The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains > >>+ a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides > >>+ debug features to trace and trigger debug transactions. There are multiple TBU > >>+ instances with each client core. > >>+ > >>+properties: > >>+ compatible: > >>+ const: qcom,qsmmuv500-tbu > > > >Why we don't have SoC specific compatibles? If that's for SDM845, then > >it should be qcom,sdm845-tbu or qcom,sdm845-qsmmuv500-tbu > > > > Because they should be all compatible (as registers). Adding a SoC compatible > might get overly-specific, but i can also see the benefits in that, so ok will > do it! > Hi Krzysztof, JFYI that the TBUs are used on our mobile SoCs going up until the SoC we commercialized in early 2022, Snapdragon 8 Gen 1. Including SDM845 there are three more premium tier SoCs using TBUs plus all of their value-tier derivatives. There will also be prior generation premium tier SoCs along with their derivatives that use the TBU as well. Does it make sense to have a target-specific compatible string given this? Thanks, Chris.