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From: Sandipan Das <sandipan.das@amd.com>
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Subject: [PATCH] KVM: x86/svm/pmu: Set PerfMonV2 global control bits correctly
Date: Fri, 1 Mar 2024 13:20:07 +0530
Message-ID: <20240301075007.644152-1-sandipan.das@amd.com>
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With PerfMonV2, a performance monitoring counter will start operating
only when both the PERF_CTLx enable bit as well as the corresponding
PerfCntrGlobalCtl enable bit are set.

When the PerfMonV2 CPUID feature bit (leaf 0x80000022 EAX bit 0) is set
for a guest but the guest kernel does not support PerfMonV2 (such as
kernels older than v5.19), the guest counters do not count since the
PerfCntrGlobalCtl MSR is initialized to zero and the guest kernel never
writes to it.

This is not observed on bare-metal as the default value of the
PerfCntrGlobalCtl MSR after a reset is 0x3f (assuming there are six
counters) and the counters can still be operated by using the enable
bit in the PERF_CTLx MSRs. Replicate the same behaviour in guests for
compatibility with older kernels.

Before:

  $ perf stat -e cycles:u true

   Performance counter stats for 'true':

                   0      cycles:u

         0.001074773 seconds time elapsed

         0.001169000 seconds user
         0.000000000 seconds sys

After:

  $ perf stat -e cycles:u true

   Performance counter stats for 'true':

             227,850      cycles:u

         0.037770758 seconds time elapsed

         0.000000000 seconds user
         0.037886000 seconds sys

Reported-by: Babu Moger <babu.moger@amd.com>
Fixes: 4a2771895ca6 ("KVM: x86/svm/pmu: Add AMD PerfMonV2 support")
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
---
 arch/x86/kvm/svm/pmu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c
index b6a7ad4d6914..14709c564d6a 100644
--- a/arch/x86/kvm/svm/pmu.c
+++ b/arch/x86/kvm/svm/pmu.c
@@ -205,6 +205,7 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
 	if (pmu->version > 1) {
 		pmu->global_ctrl_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1);
 		pmu->global_status_mask = pmu->global_ctrl_mask;
+		pmu->global_ctrl = ~pmu->global_ctrl_mask;
 	}
 
 	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;
-- 
2.34.1