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Date: Fri, 1 Mar 2024 10:15:21 +0100
From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
To: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>, 
	Geert Uytterhoeven <geert+renesas@glider.be>, Biju Das <biju.das.jz@bp.renesas.com>, 
	Magnus Damm <magnus.damm@gmail.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, 
	"linux-pwm@vger.kernel.org" <linux-pwm@vger.kernel.org>, 
	"linux-renesas-soc@vger.kernel.org" <linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v7 2/4] pwm: Add support for RZ/V2M PWM driver
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Hello Fabrizio,

your MUA introduces strange line breaks. You could do every reader of
you mails a favour and fix that. I fixed it up for my reply.

On Thu, Feb 29, 2024 at 10:45:01PM +0000, Fabrizio Castro wrote:
> > From: Uwe Kleine-K=F6nig <u.kleine-koenig@pengutronix.de>
> > Sent: Thursday, February 29, 2024 4:42 PM
> > To: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > Subject: Re: [PATCH v7 2/4] pwm: Add support for RZ/V2M PWM driver
> >=20
> > On Mon, Feb 12, 2024 at 09:06:50PM +0000, Fabrizio Castro wrote:
> > > +static inline u64 rzv2m_pwm_mul_u64_u64_div_u64_roundup(u64 a, u64 b,
> > u64 c)
> > > +{
> > > +	u64 ab =3D a * b;
> >=20
> > a * b might overflow?!
>=20
> In the context of this driver, this cannot overflow.
> The 2 formulas the above is needed for are:
> 1) period =3D (cyc + 1)*(NSEC_PER_SEC * frequency_divisor)/rate
> 2) duty_cycle =3D (cyc + 1 - low)*(NSEC_PER_SEC * frequency_divisor)/rate
>=20
> With respect to 1), the dividend overflows when period * rate also
> overflows (its product is calculated in rzv2m_pwm_config).
> However, limiting the period to a maximum value of U64_MAX / rate
> prevents the calculations from overflowing (in both directions, from peri=
od to cyc, and from cyc to period). v6 introduced max_period for this.
> The situation for 2) is very similar to 1), with duty_cycle<=3Dperiod,
> therefore limiting period to a max value (and clamping the duty cycle
> accordingly) will ensure that the calculation for duty_cycle won't
> overflow, either.

OK, so it might be right from a technical POV. From a maintainer POV
this is still bad. Authors for other drivers might copy it, or the driver
might be changed and there is no indication that the the function relies
on only be called with certain parameters.

> > > +	u64 d =3D div64_u64(ab, c);
> > > +	u64 e =3D d * c;
> > > +
> > > +	return d + ((ab - e) ? 1 : 0);
> > > +}
> > > +
> > > +static inline u64 rzv2m_pwm_mul_u64_u64_div_u64_rounddown(u64 a, u64=
 b,
> > u64 c)
> > > +{
> > > +	return div64_u64(a * b, c);
> >=20
> > ditto. This is the same function as mul_u64_u64_div_u64() isn't it?
>=20
> Since a * b cannot overflow in the case of this driver, I believe the
> above to be a better option than mul_u64_u64_div_u64.

Same technical POV vs maintainer POV as above. Plus: Even if
mul_u64_u64_div_u64 is a tad slower, reusing it has some benefits
nevertheless.
=20
> > > [...]
> > > +	cyc =3D rzv2m_pwm_read(rzv2m_pwm, RZV2M_PWMCYC);
> > > +	state->period =3D rzv2m_pwm_mul_u64_u64_div_u64_roundup(cyc + 1,
> > > +				NSEC_PER_SEC * frequency_divisor,
> > > +				rzv2m_pwm->rate);
> > > +
> > > +	low =3D rzv2m_pwm_read(rzv2m_pwm, RZV2M_PWMLOW);
> > > +	state->duty_cycle =3D rzv2m_pwm_mul_u64_u64_div_u64_roundup(cyc + 1=
 - low,
> > > +				NSEC_PER_SEC * frequency_divisor,
> > > +				rzv2m_pwm->rate);
> >=20
> > The register semantic makes me wonder if each period starts with the low
> > part. In that case the hardware called "normal" what is called inverted
> > in the pwm framework?!
>=20
> My understanding is that the PWM framework defines "normal" polarity a
> signal that starts high (and stays high) for the duration of the duty cyc=
le,
> and goes low for the remainder of the period. Conversely, a signal with
> "inversed" polarity starts low (and stays low) for the duration of the du=
ty
> cycle and goes high for the remainder of the period.

Ack.

> This IP _does_ start low, but it _doesn't_ stay low for the duration of t=
he
> duty cycle, as it then goes high for the duration of the duty cycle,
> therefore this IP doesn't perfectly fit either ("normal" or "inverted")
> definitions.
> I think you can say that the "normal" signal is _shifted_ in phase for th=
is
> IP, rather than being "inverted".

Alternatively (and a better match): What you describe is an inverted
wave form with duty_cycle =3D period - duty_cycle.

> > > +	return pm_runtime_put(chip->dev);
> >=20
> > If you evaluate the return value of pm_runtime_put() maybe check
> > pm_runtime_get_sync() for symmetry, too?
>=20
> Or I could just discard it and return 0?
> I am fine with either, what's your preference?

My preference would be to always check the return value, but given that
many drivers don't care for that, I agree to accept never checking it.
So choose one option and do it consistently please.
=20
> > > +	if (pwm_cyc && !FIELD_FIT(RZV2M_PWMCYC_PERIOD, pwm_cyc - 1))
> > > +		pwm_cyc =3D RZV2M_PWMCYC_PERIOD + 1;
> >=20
> > I don't understand the relevance of FIELD_FIT(RZV2M_PWMCYC_PERIOD,
> > pwm_cyc - 1).
>=20
> CYC is only made of 24 bits, therefore this is to make sure we don't
> go beyond a 24-bit representation.

I would have understood:

	if (FIELD_FIT(RZV2M_PWMCYC_PERIOD, pwm_cyc + 1))
		pwm_cyc =3D RZV2M_PWMCYC_PERIOD + 1;

Notice there are three changes compared to your variant:
 - drop pwm_cyc !=3D 0 check
 - drop ! from FIELD_FIT
 - pwm_cyc + 1 instead of pwm_cyc - 1

Best regards
Uwe

--=20
Pengutronix e.K.                           | Uwe Kleine-K=F6nig            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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