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From: Minda Chen <minda.chen@starfivetech.com>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
CC: Conor Dooley <conor@kernel.org>, =?iso-8859-2?Q?Krzysztof_Wilczy=F1ski?=
	<kw@linux.com>, Rob Herring <robh+dt@kernel.org>, Bjorn Helgaas
	<bhelgaas@google.com>, Thomas Gleixner <tglx@linutronix.de>, Daire McNamara
	<daire.mcnamara@microchip.com>, Emil Renner Berthing
	<emil.renner.berthing@canonical.com>, Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@linaro.org>, "devicetree@vger.kernel.org"
	<devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>, "linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>, "linux-pci@vger.kernel.org"
	<linux-pci@vger.kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer
 Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Philipp
 Zabel <p.zabel@pengutronix.de>, Mason Huo <mason.huo@starfivetech.com>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>, Kevin Xie
	<kevin.xie@starfivetech.com>
Subject: Re: [PATCH v15,RESEND 05/23] PCI: microchip: Rename two PCIe data
 structures
Thread-Topic: [PATCH v15,RESEND 05/23] PCI: microchip: Rename two PCIe data
 structures
Thread-Index: AQHaaWiyA7Q5tqIZOEWq+4FAhKnLMrEhGcSAgAGi0EA=
Date: Fri, 1 Mar 2024 11:00:41 +0000
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References: <20240227103522.80915-1-minda.chen@starfivetech.com>
 <20240227103522.80915-6-minda.chen@starfivetech.com>
 <ZeBWBfMlS4nxMZJ2@lpieralisi>
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>=20
> On Tue, Feb 27, 2024 at 06:35:04PM +0800, Minda Chen wrote:
> > Add PLDA PCIe related data structures by rename data structure name
> > from
> > mc_* to plda_*.
> >
> > axi_base_addr is stayed in struct mc_pcie for it's microchip its own da=
ta.
>=20
> Here in "for it's microchip" you mean "since it's microchip" own data.
>=20
> Please fix this "for" usage in all commit logs, I noticed it is a recurre=
nt mistake
> you make I can do it but it is tedious.
>=20
> Don't resend another version yet, I am trying to see what I can take from=
 this
> one.
>=20
Thanks. I will change this. I know the Starfive codes need time to review. =
So previous=20
I just request accept some refactoring patches first. It looks now this can=
't be achieved.=20
I will send next version in 6.9-rc1.=20
And Kevin will reply the Starfive patch(patch 21, patch 22).

> > The event interrupt codes is still using struct mc_pcie because the
> > event
>=20
> "code", please not "codes". Please fix it everywhere in your patch series=
, same
> as above.
>=20
> Lorenzo
>=20
I will check all the commit message.

> > interrupt codes can not be re-used.
> >
> > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >  .../pci/controller/plda/pcie-microchip-host.c | 96
> > ++++++++++---------
> >  1 file changed, 53 insertions(+), 43 deletions(-)
> >
> > diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c
> > b/drivers/pci/controller/plda/pcie-microchip-host.c
> > index c55ede80a6d0..df0736f688ce 100644
> > --- a/drivers/pci/controller/plda/pcie-microchip-host.c
> > +++ b/drivers/pci/controller/plda/pcie-microchip-host.c
> > @@ -22,7 +22,7 @@
> >  #include "pcie-plda.h"
> >
> >  /* Number of MSI IRQs */
> > -#define MC_MAX_NUM_MSI_IRQS			32
> > +#define PLDA_MAX_NUM_MSI_IRQS			32
> >
> >  /* PCIe Bridge Phy and Controller Phy offsets */
> >  #define MC_PCIE1_BRIDGE_ADDR			0x00008000u
> > @@ -179,25 +179,29 @@ struct event_map {
> >  	u32 event_bit;
> >  };
> >
> > -struct mc_msi {
> > +struct plda_msi {
> >  	struct mutex lock;		/* Protect used bitmap */
> >  	struct irq_domain *msi_domain;
> >  	struct irq_domain *dev_domain;
> >  	u32 num_vectors;
> >  	u64 vector_phy;
> > -	DECLARE_BITMAP(used, MC_MAX_NUM_MSI_IRQS);
> > +	DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS);
> >  };
> >
> > -struct mc_pcie {
> > -	void __iomem *axi_base_addr;
> > +struct plda_pcie_rp {
> >  	struct device *dev;
> >  	struct irq_domain *intx_domain;
> >  	struct irq_domain *event_domain;
> >  	raw_spinlock_t lock;
> > -	struct mc_msi msi;
> > +	struct plda_msi msi;
> >  	void __iomem *bridge_addr;
> >  };
> >
> > +struct mc_pcie {
> > +	struct plda_pcie_rp plda;
> > +	void __iomem *axi_base_addr;
> > +};
> > +
> >  struct cause {
> >  	const char *sym;
> >  	const char *str;
> > @@ -313,7 +317,7 @@ static struct mc_pcie *port;
> >
> >  static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem
> > *ecam)  {
> > -	struct mc_msi *msi =3D &port->msi;
> > +	struct plda_msi *msi =3D &port->plda.msi;
> >  	u16 reg;
> >  	u8 queue_size;
> >
> > @@ -336,10 +340,10 @@ static void mc_pcie_enable_msi(struct mc_pcie
> > *port, void __iomem *ecam)
> >
> >  static void mc_handle_msi(struct irq_desc *desc)  {
> > -	struct mc_pcie *port =3D irq_desc_get_handler_data(desc);
> > +	struct plda_pcie_rp *port =3D irq_desc_get_handler_data(desc);
> >  	struct irq_chip *chip =3D irq_desc_get_chip(desc);
> >  	struct device *dev =3D port->dev;
> > -	struct mc_msi *msi =3D &port->msi;
> > +	struct plda_msi *msi =3D &port->msi;
> >  	void __iomem *bridge_base_addr =3D port->bridge_addr;
> >  	unsigned long status;
> >  	u32 bit;
> > @@ -364,7 +368,7 @@ static void mc_handle_msi(struct irq_desc *desc)
> >
> >  static void mc_msi_bottom_irq_ack(struct irq_data *data)  {
> > -	struct mc_pcie *port =3D irq_data_get_irq_chip_data(data);
> > +	struct plda_pcie_rp *port =3D irq_data_get_irq_chip_data(data);
> >  	void __iomem *bridge_base_addr =3D port->bridge_addr;
> >  	u32 bitpos =3D data->hwirq;
> >
> > @@ -373,7 +377,7 @@ static void mc_msi_bottom_irq_ack(struct irq_data
> > *data)
> >
> >  static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg
> > *msg)  {
> > -	struct mc_pcie *port =3D irq_data_get_irq_chip_data(data);
> > +	struct plda_pcie_rp *port =3D irq_data_get_irq_chip_data(data);
> >  	phys_addr_t addr =3D port->msi.vector_phy;
> >
> >  	msg->address_lo =3D lower_32_bits(addr); @@ -400,8 +404,8 @@ static
> > struct irq_chip mc_msi_bottom_irq_chip =3D {  static int
> > mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
> >  				   unsigned int nr_irqs, void *args)  {
> > -	struct mc_pcie *port =3D domain->host_data;
> > -	struct mc_msi *msi =3D &port->msi;
> > +	struct plda_pcie_rp *port =3D domain->host_data;
> > +	struct plda_msi *msi =3D &port->msi;
> >  	unsigned long bit;
> >
> >  	mutex_lock(&msi->lock);
> > @@ -425,8 +429,8 @@ static void mc_irq_msi_domain_free(struct
> irq_domain *domain, unsigned int virq,
> >  				   unsigned int nr_irqs)
> >  {
> >  	struct irq_data *d =3D irq_domain_get_irq_data(domain, virq);
> > -	struct mc_pcie *port =3D irq_data_get_irq_chip_data(d);
> > -	struct mc_msi *msi =3D &port->msi;
> > +	struct plda_pcie_rp *port =3D irq_data_get_irq_chip_data(d);
> > +	struct plda_msi *msi =3D &port->msi;
> >
> >  	mutex_lock(&msi->lock);
> >
> > @@ -456,11 +460,11 @@ static struct msi_domain_info
> mc_msi_domain_info =3D {
> >  	.chip =3D &mc_msi_irq_chip,
> >  };
> >
> > -static int mc_allocate_msi_domains(struct mc_pcie *port)
> > +static int mc_allocate_msi_domains(struct plda_pcie_rp *port)
> >  {
> >  	struct device *dev =3D port->dev;
> >  	struct fwnode_handle *fwnode =3D of_node_to_fwnode(dev->of_node);
> > -	struct mc_msi *msi =3D &port->msi;
> > +	struct plda_msi *msi =3D &port->msi;
> >
> >  	mutex_init(&port->msi.lock);
> >
> > @@ -484,7 +488,7 @@ static int mc_allocate_msi_domains(struct mc_pcie
> > *port)
> >
> >  static void mc_handle_intx(struct irq_desc *desc)  {
> > -	struct mc_pcie *port =3D irq_desc_get_handler_data(desc);
> > +	struct plda_pcie_rp *port =3D irq_desc_get_handler_data(desc);
> >  	struct irq_chip *chip =3D irq_desc_get_chip(desc);
> >  	struct device *dev =3D port->dev;
> >  	void __iomem *bridge_base_addr =3D port->bridge_addr; @@ -511,7 +515,=
7
> > @@ static void mc_handle_intx(struct irq_desc *desc)
> >
> >  static void mc_ack_intx_irq(struct irq_data *data)  {
> > -	struct mc_pcie *port =3D irq_data_get_irq_chip_data(data);
> > +	struct plda_pcie_rp *port =3D irq_data_get_irq_chip_data(data);
> >  	void __iomem *bridge_base_addr =3D port->bridge_addr;
> >  	u32 mask =3D BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT);
> >
> > @@ -520,7 +524,7 @@ static void mc_ack_intx_irq(struct irq_data *data)
> >
> >  static void mc_mask_intx_irq(struct irq_data *data)  {
> > -	struct mc_pcie *port =3D irq_data_get_irq_chip_data(data);
> > +	struct plda_pcie_rp *port =3D irq_data_get_irq_chip_data(data);
> >  	void __iomem *bridge_base_addr =3D port->bridge_addr;
> >  	unsigned long flags;
> >  	u32 mask =3D BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); @@ -535,7
> > +539,7 @@ static void mc_mask_intx_irq(struct irq_data *data)
> >
> >  static void mc_unmask_intx_irq(struct irq_data *data)  {
> > -	struct mc_pcie *port =3D irq_data_get_irq_chip_data(data);
> > +	struct plda_pcie_rp *port =3D irq_data_get_irq_chip_data(data);
> >  	void __iomem *bridge_base_addr =3D port->bridge_addr;
> >  	unsigned long flags;
> >  	u32 mask =3D BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); @@ -625,21
> > +629,22 @@ static u32 local_events(struct mc_pcie *port)
> >  	return val;
> >  }
> >
> > -static u32 get_events(struct mc_pcie *port)
> > +static u32 get_events(struct plda_pcie_rp *port)
> >  {
> > +	struct mc_pcie *mc_port =3D container_of(port, struct mc_pcie, plda);
> >  	u32 events =3D 0;
> >
> > -	events |=3D pcie_events(port);
> > -	events |=3D sec_errors(port);
> > -	events |=3D ded_errors(port);
> > -	events |=3D local_events(port);
> > +	events |=3D pcie_events(mc_port);
> > +	events |=3D sec_errors(mc_port);
> > +	events |=3D ded_errors(mc_port);
> > +	events |=3D local_events(mc_port);
> >
> >  	return events;
> >  }
> >
> >  static irqreturn_t mc_event_handler(int irq, void *dev_id)  {
> > -	struct mc_pcie *port =3D dev_id;
> > +	struct plda_pcie_rp *port =3D dev_id;
> >  	struct device *dev =3D port->dev;
> >  	struct irq_data *data;
> >
> > @@ -655,7 +660,7 @@ static irqreturn_t mc_event_handler(int irq, void
> > *dev_id)
> >
> >  static void mc_handle_event(struct irq_desc *desc)  {
> > -	struct mc_pcie *port =3D irq_desc_get_handler_data(desc);
> > +	struct plda_pcie_rp *port =3D irq_desc_get_handler_data(desc);
> >  	unsigned long events;
> >  	u32 bit;
> >  	struct irq_chip *chip =3D irq_desc_get_chip(desc); @@ -672,12 +677,13
> > @@ static void mc_handle_event(struct irq_desc *desc)
> >
> >  static void mc_ack_event_irq(struct irq_data *data)  {
> > -	struct mc_pcie *port =3D irq_data_get_irq_chip_data(data);
> > +	struct plda_pcie_rp *port =3D irq_data_get_irq_chip_data(data);
> > +	struct mc_pcie *mc_port =3D container_of(port, struct mc_pcie, plda);
> >  	u32 event =3D data->hwirq;
> >  	void __iomem *addr;
> >  	u32 mask;
> >
> > -	addr =3D port->axi_base_addr + event_descs[event].base +
> > +	addr =3D mc_port->axi_base_addr + event_descs[event].base +
> >  		event_descs[event].offset;
> >  	mask =3D event_descs[event].mask;
> >  	mask |=3D event_descs[event].enb_mask; @@ -687,13 +693,14 @@ static
> > void mc_ack_event_irq(struct irq_data *data)
> >
> >  static void mc_mask_event_irq(struct irq_data *data)  {
> > -	struct mc_pcie *port =3D irq_data_get_irq_chip_data(data);
> > +	struct plda_pcie_rp *port =3D irq_data_get_irq_chip_data(data);
> > +	struct mc_pcie *mc_port =3D container_of(port, struct mc_pcie, plda);
> >  	u32 event =3D data->hwirq;
> >  	void __iomem *addr;
> >  	u32 mask;
> >  	u32 val;
> >
> > -	addr =3D port->axi_base_addr + event_descs[event].base +
> > +	addr =3D mc_port->axi_base_addr + event_descs[event].base +
> >  		event_descs[event].mask_offset;
> >  	mask =3D event_descs[event].mask;
> >  	if (event_descs[event].enb_mask) {
> > @@ -717,13 +724,14 @@ static void mc_mask_event_irq(struct irq_data
> > *data)
> >
> >  static void mc_unmask_event_irq(struct irq_data *data)  {
> > -	struct mc_pcie *port =3D irq_data_get_irq_chip_data(data);
> > +	struct plda_pcie_rp *port =3D irq_data_get_irq_chip_data(data);
> > +	struct mc_pcie *mc_port =3D container_of(port, struct mc_pcie, plda);
> >  	u32 event =3D data->hwirq;
> >  	void __iomem *addr;
> >  	u32 mask;
> >  	u32 val;
> >
> > -	addr =3D port->axi_base_addr + event_descs[event].base +
> > +	addr =3D mc_port->axi_base_addr + event_descs[event].base +
> >  		event_descs[event].mask_offset;
> >  	mask =3D event_descs[event].mask;
> >
> > @@ -811,7 +819,7 @@ static int mc_pcie_init_clks(struct device *dev)
> >  	return 0;
> >  }
> >
> > -static int mc_pcie_init_irq_domains(struct mc_pcie *port)
> > +static int mc_pcie_init_irq_domains(struct plda_pcie_rp *port)
> >  {
> >  	struct device *dev =3D port->dev;
> >  	struct device_node *node =3D dev->of_node; @@ -889,7 +897,7 @@ static
> > void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,
> > }
> >
> >  static int mc_pcie_setup_windows(struct platform_device *pdev,
> > -				 struct mc_pcie *port)
> > +				 struct plda_pcie_rp *port)
> >  {
> >  	void __iomem *bridge_base_addr =3D port->bridge_addr;
> >  	struct pci_host_bridge *bridge =3D platform_get_drvdata(pdev); @@
> > -970,7 +978,7 @@ static void mc_disable_interrupts(struct mc_pcie *port=
)
> >  	writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST);  }
> >
> > -static int mc_init_interrupts(struct platform_device *pdev, struct
> > mc_pcie *port)
> > +static int mc_init_interrupts(struct platform_device *pdev, struct
> > +plda_pcie_rp *port)
> >  {
> >  	struct device *dev =3D &pdev->dev;
> >  	int irq;
> > @@ -1043,12 +1051,12 @@ static int mc_platform_init(struct
> pci_config_window *cfg)
> >  	mc_pcie_enable_msi(port, cfg->win);
> >
> >  	/* Configure non-config space outbound ranges */
> > -	ret =3D mc_pcie_setup_windows(pdev, port);
> > +	ret =3D mc_pcie_setup_windows(pdev, &port->plda);
> >  	if (ret)
> >  		return ret;
> >
> >  	/* Address translation is up; safe to enable interrupts */
> > -	ret =3D mc_init_interrupts(pdev, port);
> > +	ret =3D mc_init_interrupts(pdev, &port->plda);
> >  	if (ret)
> >  		return ret;
> >
> > @@ -1059,6 +1067,7 @@ static int mc_host_probe(struct platform_device
> > *pdev)  {
> >  	struct device *dev =3D &pdev->dev;
> >  	void __iomem *bridge_base_addr;
> > +	struct plda_pcie_rp *plda;
> >  	int ret;
> >  	u32 val;
> >
> > @@ -1066,7 +1075,8 @@ static int mc_host_probe(struct platform_device
> *pdev)
> >  	if (!port)
> >  		return -ENOMEM;
> >
> > -	port->dev =3D dev;
> > +	plda =3D &port->plda;
> > +	plda->dev =3D dev;
> >
> >  	port->axi_base_addr =3D devm_platform_ioremap_resource(pdev, 1);
> >  	if (IS_ERR(port->axi_base_addr))
> > @@ -1075,7 +1085,7 @@ static int mc_host_probe(struct platform_device
> *pdev)
> >  	mc_disable_interrupts(port);
> >
> >  	bridge_base_addr =3D port->axi_base_addr + MC_PCIE_BRIDGE_ADDR;
> > -	port->bridge_addr =3D bridge_base_addr;
> > +	plda->bridge_addr =3D bridge_base_addr;
> >
> >  	/* Allow enabling MSI by disabling MSI-X */
> >  	val =3D readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); @@ -1087,10
> > +1097,10 @@ static int mc_host_probe(struct platform_device *pdev)
> >  	val &=3D NUM_MSI_MSGS_MASK;
> >  	val >>=3D NUM_MSI_MSGS_SHIFT;
> >
> > -	port->msi.num_vectors =3D 1 << val;
> > +	plda->msi.num_vectors =3D 1 << val;
> >
> >  	/* Pick vector address from design */
> > -	port->msi.vector_phy =3D readl_relaxed(bridge_base_addr + IMSI_ADDR);
> > +	plda->msi.vector_phy =3D readl_relaxed(bridge_base_addr + IMSI_ADDR);
> >
> >  	ret =3D mc_pcie_init_clks(dev);
> >  	if (ret) {
> > --
> > 2.17.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv