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Fri, 1 Mar 2024 18:50:00 GMT Received: from [10.110.82.174] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 1 Mar 2024 10:49:57 -0800 Message-ID: <6a3e3071-f8cd-66b4-99a0-427f7e11177a@quicinc.com> Date: Fri, 1 Mar 2024 10:49:57 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v7 11/12] firmware: qcom: scm: clarify the comment in qcom_scm_pas_init_image() To: Bjorn Andersson , Bartosz Golaszewski CC: Andy Gross , Konrad Dybcio , Elliot Berman , Krzysztof Kozlowski , Guru Das Srinagesh , Andrew Halaney , "Maximilian Luz" , Alex Elder , "Srini Kandagatla" , Arnd Bergmann , , , , , "Bartosz Golaszewski" , Deepti Jaggi References: <20240205182810.58382-1-brgl@bgdev.pl> <20240205182810.58382-12-brgl@bgdev.pl> Content-Language: en-US From: Prasad Sodagudi In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: zJU114Lht-Ax-EGW8-ctMDqs437U1DQF X-Proofpoint-GUID: zJU114Lht-Ax-EGW8-ctMDqs437U1DQF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-01_20,2024-03-01_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 suspectscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403010153 On 2/17/2024 7:50 PM, Bjorn Andersson wrote: > On Mon, Feb 05, 2024 at 07:28:09PM +0100, Bartosz Golaszewski wrote: >> From: Bartosz Golaszewski >> >> The "memory protection" mechanism mentioned in the comment is the SHM >> Bridge. This is also the reason why we do not convert this call to using >> the TZ memory allocator. >> > No, this mechanism predates shmbridge. Yes. PIL calls are there for very long time and shm bridge concept is introduced later. > >> Signed-off-by: Bartosz Golaszewski >> Tested-by: Andrew Halaney # sc8280xp-lenovo-thinkpad-x13s >> Tested-by: Deepti Jaggi #sa8775p-ride >> Reviewed-by: Elliot Berman >> --- >> drivers/firmware/qcom/qcom_scm.c | 10 +++++++--- >> 1 file changed, 7 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c >> index 839773270a21..7ba5cff6e4e7 100644 >> --- a/drivers/firmware/qcom/qcom_scm.c >> +++ b/drivers/firmware/qcom/qcom_scm.c >> @@ -563,9 +563,13 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, >> struct qcom_scm_res res; >> >> /* >> - * During the scm call memory protection will be enabled for the meta >> - * data blob, so make sure it's physically contiguous, 4K aligned and >> - * non-cachable to avoid XPU violations. > What this is saying is that the memory will be made unaccessible to > Linux, so it needs to be contiguous and aligned. Based on my understanding,  this buffer has to be  physically contiguous, 4K aligned and non-cachable to avoid XPU violations. We should keep this comment > >> + * During the SCM call the hypervisor will make the buffer containing >> + * the program data into an SHM Bridge. > Are you saying that the hypervisor will convert this memory to a > shmbridge, and then pass it to TrustZone? Yes.  Specifically for PIL calls hyp is creating shm bridge for buffers/regions on behalf of Linux/NS-EL1. > >> This is why we exceptionally >> + * must not use the TrustZone memory allocator here as - depending on >> + * Kconfig - it may already use the SHM Bridge mechanism internally. >> + * > "it may already"? You describe above that we shouldn't pass shmbridge > memory, and the other case never deals with shmbridges. So, I think you > can omit this part. > >> + * If we pass a buffer that is already part of an SHM Bridge to this >> + * call, it will fail. > Could this be because the consumer of this buffer operates in EL2, and > not TZ? These buffers are consumed by TZ only and not by EL2.  hyp creating the required bridges for pil buffers. > > Regards, > Bjorn > >> */ >> mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys, >> GFP_KERNEL); >> -- >> 2.40.1 >>