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AJvYcCVmxDxw9sE+0DCqgcLrNXUglzvKe6c9ca1s1aV7eV/5GOiIS+KI/iNbVvTTGfF43hC6M5w9Jczhuz8LtGd9eQVMWinnVSg1vWoJUWkb X-Gm-Message-State: AOJu0YxzGM9irLJF+1JAy6vX4gmiCuf5ma9oNe06EPsqCOkgwnynH3/a lReQBnYKWgkAJrl4BW6by5GG31/PAiTRFCul5FZ486tTq1/Nd+A6yK9odFYP2gKRwshiHVk6npa 7YZI4Vucm4tErqqns0dU/rxMJ8xkNnzo1SWJu X-Received: by 2002:a05:6402:5215:b0:566:f626:229b with SMTP id s21-20020a056402521500b00566f626229bmr28826edd.7.1709321067574; Fri, 01 Mar 2024 11:24:27 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240301074423.643779-1-sandipan.das@amd.com> In-Reply-To: <20240301074423.643779-1-sandipan.das@amd.com> From: Jim Mattson Date: Fri, 1 Mar 2024 11:24:11 -0800 Message-ID: Subject: Re: [PATCH] KVM: x86: Do not mask LVTPC when handling a PMI on AMD platforms To: Sandipan Das Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, seanjc@google.com, pbonzini@redhat.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, mlevitsk@redhat.com, vkuznets@redhat.com, mizhang@google.com, tao1.su@linux.intel.com, andriy.shevchenko@linux.intel.com, ravi.bangoria@amd.com, ananth.narayan@amd.com, nikunj.dadhania@amd.com, santosh.shukla@amd.com, manali.shukla@amd.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Feb 29, 2024 at 11:44=E2=80=AFPM Sandipan Das wrote: > > On AMD and Hygon platforms, the local APIC does not automatically set > the mask bit of the LVTPC register when handling a PMI and there is > no need to clear it in the kernel's PMI handler. I don't know why it didn't occur to me that different x86 vendors wouldn't agree on this specification. :) > For guests, the mask bit is currently set by kvm_apic_local_deliver() > and unless it is cleared by the guest kernel's PMI handler, PMIs stop > arriving and break use-cases like sampling with perf record. > > This does not affect non-PerfMonV2 guests because PMIs are handled in > the guest kernel by x86_pmu_handle_irq() which always clears the LVTPC > mask bit irrespective of the vendor. > > Before: > > $ perf record -e cycles:u true > [ perf record: Woken up 1 times to write data ] > [ perf record: Captured and wrote 0.001 MB perf.data (1 samples) ] > > After: > > $ perf record -e cycles:u true > [ perf record: Woken up 1 times to write data ] > [ perf record: Captured and wrote 0.002 MB perf.data (19 samples) ] > > Fixes: a16eb25b09c0 ("KVM: x86: Mask LVTPC when handling a PMI") > Signed-off-by: Sandipan Das > --- > arch/x86/kvm/lapic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 3242f3da2457..0959a887c306 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2768,7 +2768,7 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, = int lvt_type) > trig_mode =3D reg & APIC_LVT_LEVEL_TRIGGER; > > r =3D __apic_accept_irq(apic, mode, vector, 1, trig_mode,= NULL); > - if (r && lvt_type =3D=3D APIC_LVTPC) > + if (r && lvt_type =3D=3D APIC_LVTPC && !guest_cpuid_is_am= d_or_hygon(apic->vcpu)) Perhaps we could use a positive predicate instead: guest_cpuid_is_intel(apic->vcpu)? > kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LV= T_MASKED); > return r; > } > -- > 2.34.1 Reviewed-by: Jim Mattson