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Date: Sat, 2 Mar 2024 08:35:10 +0100
From: Andrew Jones <ajones@ventanamicro.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: linux-riscv@lists.infradead.org, Albert Ou <aou@eecs.berkeley.edu>, 
	Alexandre Ghiti <alexghiti@rivosinc.com>, Anup Patel <apatel@ventanamicro.com>, 
	Dylan Jhong <dylan@andestech.com>, Jisheng Zhang <jszhang@kernel.org>, 
	Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, 
	Sergey Matyukevich <sergey.matyukevich@syntacore.com>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: mm: Fix prototype to avoid discarding const
Message-ID: <20240302-84b126d91dac9f73f5efebaa@orel>
References: <20240301201837.2826172-1-samuel.holland@sifive.com>
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In-Reply-To: <20240301201837.2826172-1-samuel.holland@sifive.com>

On Fri, Mar 01, 2024 at 12:18:32PM -0800, Samuel Holland wrote:
> __flush_tlb_range() does not modify the provided cpumask, so its cmask
> parameter can be pointer-to-const. This avoids the unsafe cast of
> cpu_online_mask.
> 
> Fixes: 54d7431af73e ("riscv: Add support for BATCHED_UNMAP_TLB_FLUSH")
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
>  arch/riscv/mm/tlbflush.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 893566e004b7..07d743f87b3f 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -99,7 +99,7 @@ static void __ipi_flush_tlb_range_asid(void *info)
>  	local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid);
>  }
>  
> -static void __flush_tlb_range(struct cpumask *cmask, unsigned long asid,
> +static void __flush_tlb_range(const struct cpumask *cmask, unsigned long asid,
>  			      unsigned long start, unsigned long size,
>  			      unsigned long stride)
>  {
> @@ -200,7 +200,7 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
>  
>  void flush_tlb_kernel_range(unsigned long start, unsigned long end)
>  {
> -	__flush_tlb_range((struct cpumask *)cpu_online_mask, FLUSH_TLB_NO_ASID,
> +	__flush_tlb_range(cpu_online_mask, FLUSH_TLB_NO_ASID,
>  			  start, end - start, PAGE_SIZE);
>  }
>  
> -- 
> 2.43.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>