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References: <20231013181712.2128037-1-jernej.skrabec@gmail.com>
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Reply-To: wens@csie.org
From: Chen-Yu Tsai <wens@csie.org>
Date: Sat, 2 Mar 2024 19:42:11 +0800
Message-ID: <CAGb2v651T28yrkaAbX3ckV8gEsYXdGgHMgCb3Jdmbej2OnNyLQ@mail.gmail.com>
Subject: Re: [PATCH] clk: sunxi-ng: h6: Reparent CPUX during PLL CPUX rate change
To: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: samuel@sholland.org, sboyd@kernel.org, linux-clk@vger.kernel.org, 
	linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, 
	linux-kernel@vger.kernel.org, Chad Wagner <wagnerch42@gmail.com>
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On Sat, Oct 14, 2023 at 2:17=E2=80=AFAM Jernej Skrabec <jernej.skrabec@gmai=
l.com> wrote:
>
> While PLL CPUX clock rate change when CPU is running from it works in
> vast majority of cases, now and then it causes instability. This leads
> to system crashes and other undefined behaviour. After a lot of testing
> (30+ hours) while also doing a lot of frequency switches, we can't
> observe any instability issues anymore when doing reparenting to stable
> clock like 24 MHz oscillator.
>
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU=
")
> Reported-by: Chad Wagner <wagnerch42@gmail.com>
> Link: https://forum.libreelec.tv/thread/27295-orange-pi-3-lts-freezes/
> Tested-by: Chad Wagner <wagnerch42@gmail.com>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>