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From: Frank Li <Frank.Li@nxp.com>
Date: Sat, 02 Mar 2024 11:27:44 -0500
Subject: [PATCH v2 1/4] arm64: dts: imx8: add cm40 subsystem dtsi
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To: Rob Herring <robh@kernel.org>, 
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 Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, 
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 Fabio Estevam <festevam@gmail.com>
Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, 
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 
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 =?utf-8?B?K2dtVjA4UERBenhJOUFtTjJ5M2M4WTVSck1kdHd4QVhxcGpaVVZ1ZS8yWStX?=
 =?utf-8?B?bWY5ZVBwNU5wazRnMkVYa1pYL1hscWJqM1JBOEZyTW9BcmFEWGsxT0JJYkIy?=
 =?utf-8?B?S3krZkJnbllkK244dUg2aUI3QmxZdVFNWUgvakpDZ0JxeFFiL01LV2dtSFFS?=
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 =?utf-8?B?YUM4MW1EeHhDdThBMFQrbnFuc3pmZGJxUkVwOFd0WFk4NGZ3Qk9YQ3g0OXJ3?=
 =?utf-8?B?SWNMcStRVStiMHJqdlFYcDArUEE0eEYzMk9VM1J4djNEbVo4ME55V0MydzVU?=
 =?utf-8?B?RC95bU5iWXJnSEtYUVVJRTNmUDFtOXp6ZC9aOXJERkZieS9iZkMxd2hHT2ta?=
 =?utf-8?B?NzcvR1FCTXdwVnRQMXhGUlEweFJJd2R5YU93VFFlRVZiWjdGV0ZlaElNTXJC?=
 =?utf-8?B?WHNGdlp2dGt2WFA1S3ptOGZaRHdmQWhBK1d3M09wZittS3FaV3FvSUZEYlVZ?=
 =?utf-8?B?TW9NakNTQjZReHJQdVJEbVhOZnJ0S1pHTFdSM2x5Sk9Ta0hJbHl4Q2pQOEJL?=
 =?utf-8?B?WTJHbGJzcjFsN3g3MktVV09RZnJ2VjhrY0RmUHJEOWEyQ3QvRjRHNmtiTHlv?=
 =?utf-8?B?YmVSWDQyMnd3SE1HVnBNUnlHdU9QbjZEc0JLNnJIayt1WFI2akhDYy9kbmJi?=
 =?utf-8?B?VWZuZi9tK2k3a0ZVMUp0STQrWlVFS2tnRzZFSTRFZFI4OGUxK1hKT3dnZTlR?=
 =?utf-8?B?UzRFd2pjVFhsMGszTDlSQ0pPdFM4OUEwVWwxZWhLVUNWY2hYRTM2V2ZTdkJw?=
 =?utf-8?B?ZzFDcnc3QjByaDlHMmVYWEZxMEhZQldMVThQcm9qRUJ0Ynh4U2d6RHhKZ082?=
 =?utf-8?B?MGE1MjV4MkJuSm51RXFrd3NaQXlyeVBnaXJXK2toZFh1LzlXRGhmMDFJbXNo?=
 =?utf-8?B?bEY2UTAwaXVVbTdKa3NBTVovTmlTVi9XWkZoN04rdmZVWXI0OGpYZW9Fa1dx?=
 =?utf-8?B?cm9EN3pYK2h1OThhckRpZWNTU2dBdDExRjhtMXo4R1dxQzF5ZkhJZWlLcFI3?=
 =?utf-8?B?b3duV0J2cE9iOVdQZ1B0OEdKNXA3LzE0UVEwWlRGSUl1VmU4Z0ZOTGNVdS94?=
 =?utf-8?B?Nmg2TG8vUENxYXgwOFpXQnp3MWRKcjlWbHArQnRFOFZBVmptOS8xazlpRmxT?=
 =?utf-8?B?cXoySnFLMW9tUGRnRUVmV1MzTVZLR0c4RG5hT05yWGhqb0ZMdjNSdlNaVUh6?=
 =?utf-8?B?QWNtVnRhZ202T0g5WEhpRXhJSk9DWTl3ZHoyL2dmR2MxYUxURTNCOGkwdmRr?=
 =?utf-8?B?UG8zUE8wTXlTQmxUMDJGTjk0Nis4b3ZJYnpVbVJwbHNYOUVLOGxjMGhQSVJq?=
 =?utf-8?B?Ym96OVRGa21OdHhvWkNaeWoyM1piQXJ2WGVtblo4SHZIMDc2Sldmay9nQzN5?=
 =?utf-8?B?ZUFEUHQrdGYvbHFVdG44cWNIQ3VGZUE2MTRlWjdDWFlMdVRsNUVzQ2lXbW5z?=
 =?utf-8?B?TThLZC9kYVlZYlNBQzFwaEN1aTdMVUtFZW1WTXNWaWFWdXVCSHdmSXBVanJR?=
 =?utf-8?B?MEVhd1Z3YU9pbFVxWjNmK1R6MGtxRkhSUlJwcnZ1cU4xb05RZ0NSRDJqdi9L?=
 =?utf-8?B?dVRxa0dIYWN5L3c1K0ZqTUVCanVzVUt1c095Y3pnRG5oK21saEFqeVEzV29K?=
 =?utf-8?B?NDdSOW5vQnJmQVR5T0R1bW9kdUVCWDM4Szg2Ky8yYkdJK3RZL2tnNmNtU3Y4?=
 =?utf-8?B?amgyeXlCSFg1L2J5TENnbnVWTm16azlSOXZtaEJmdHdsaEU3VTZCWlpkRXFO?=
 =?utf-8?B?NjBNVkp1OGk5YWIvRXlVcDNCM25udS9ETHd2T1EzekhOakNRK1haT0hlSk5N?=
 =?utf-8?B?eFhKbUllblNOV0ZzdmYzd05qVlFtWUtSWExHTHh3eGdDOVNaNDF4cmh4NXlX?=
 =?utf-8?B?L2tseEtXVFFzNm9yTzZlTDJvV05tT1VCSkRJTnhyZzhVdDJ4L1daVlBJMEY4?=
 =?utf-8?Q?1nGs=3D?=
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From: Dong Aisheng <aisheng.dong@nxp.com>

Add cm40 subsystem dtsi.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8dxl.dtsi      |  2 +
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi      |  1 +
 3 files changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
new file mode 100644
index 0000000000000..68043ab74e765
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+cm40_ipg_clk: clock-cm40-ipg {
+	compatible = "fixed-clock";
+	#clock-cells = <0>;
+	clock-frequency = <132000000>;
+	clock-output-names = "cm40_ipg_clk";
+};
+
+cm40_subsys: bus@34000000 {
+	compatible = "simple-bus";
+	interrupt-parent = <&cm40_intmux>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x34000000 0x0 0x34000000 0x4000000>;
+
+	cm40_i2c: i2c@37230000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x37230000 0x1000>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cm40_i2c_lpcg 0>,
+			 <&cm40_i2c_lpcg 1>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+		status = "disabled";
+	};
+
+	cm40_intmux: intmux@37400000 {
+		compatible = "fsl,imx-intmux";
+		reg = <0x37400000 0x1000>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&cm40_ipg_clk>;
+		clock-names = "ipg";
+		power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
+		status = "disabled";
+	};
+
+	cm40_i2c_lpcg: clock-controller@37630000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x37630000 0x1000>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
+			 <&cm40_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "cm40_lpcg_i2c_clk",
+				     "cm40_lpcg_i2c_ipg_clk";
+		power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index a0674c5c55766..9d49c75a26222 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/clock/imx8-clock.h>
 #include <dt-bindings/dma/fsl-edma.h>
+#include <dt-bindings/clock/imx8-lpcg.h>
 #include <dt-bindings/firmware/imx/rsrc.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
 	};
 
 	/* sorted in register address */
+	#include "imx8-ss-cm40.dtsi"
 	#include "imx8-ss-adma.dtsi"
 	#include "imx8-ss-conn.dtsi"
 	#include "imx8-ss-ddr.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 10e16d84c0c3b..0313f295de2e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -317,6 +317,7 @@ map0 {
 	/* sorted in register address */
 	#include "imx8-ss-img.dtsi"
 	#include "imx8-ss-vpu.dtsi"
+	#include "imx8-ss-cm40.dtsi"
 	#include "imx8-ss-gpu0.dtsi"
 	#include "imx8-ss-adma.dtsi"
 	#include "imx8-ss-conn.dtsi"

-- 
2.34.1