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From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, linux-arm-kernel@lists.infradead.org, Frank Li <Frank.Li@nxp.com>
Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dong Aisheng <aisheng.dong@nxp.com>, Frank Li <Frank.Li@nxp.com>
Subject: Re: [PATCH v2 1/4] arm64: dts: imx8: add cm40 subsystem dtsi
Date: Mon, 04 Mar 2024 10:11:57 +0100
Message-ID: <5761273.DvuYhMxLoT@steina-w>
Organization: TQ-Systems GmbH
In-Reply-To: <20240302-m4_lpuart-v2-1-89a5952043b6@nxp.com>
References: <20240302-m4_lpuart-v2-0-89a5952043b6@nxp.com> <20240302-m4_lpuart-v2-1-89a5952043b6@nxp.com>
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Hi Frank,

thanks for the update.

Am Samstag, 2. M=E4rz 2024, 17:27:44 CET schrieb Frank Li:
> From: Dong Aisheng <aisheng.dong@nxp.com>
>=20
> Add cm40 subsystem dtsi.
>=20
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++=
++++++
>  arch/arm64/boot/dts/freescale/imx8dxl.dtsi      |  2 +
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi      |  1 +
>  3 files changed, 70 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64=
/boot/dts/freescale/imx8-ss-cm40.dtsi
> new file mode 100644
> index 0000000000000..68043ab74e765
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + *	Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +cm40_ipg_clk: clock-cm40-ipg {
> +	compatible =3D "fixed-clock";
> +	#clock-cells =3D <0>;
> +	clock-frequency =3D <132000000>;
> +	clock-output-names =3D "cm40_ipg_clk";
> +};
> +
> +cm40_subsys: bus@34000000 {
> +	compatible =3D "simple-bus";
> +	interrupt-parent =3D <&cm40_intmux>;

I would have put that below ranges, but it might be just personal preferenc=
e.

> +	#address-cells =3D <1>;
> +	#size-cells =3D <1>;
> +	ranges =3D <0x34000000 0x0 0x34000000 0x4000000>;
> +
> +	cm40_i2c: i2c@37230000 {
> +		compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg =3D <0x37230000 0x1000>;
> +		interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks =3D <&cm40_i2c_lpcg 0>,
> +			 <&cm40_i2c_lpcg 1>;
> +		clock-names =3D "per", "ipg";
> +		assigned-clocks =3D <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates =3D <24000000>;
> +		power-domains =3D <&pd IMX_SC_R_M4_0_I2C>;
> +		status =3D "disabled";
> +	};
> +
> +	cm40_intmux: intmux@37400000 {
> +		compatible =3D "fsl,imx-intmux";
> +		reg =3D <0x37400000 0x1000>;
> +		interrupts =3D <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-controller;
> +		interrupt-parent =3D <&gic>;

Please put this above interrupt property, you are mixing interrupt
properties of the device itself with interrupt-controller properties.

With these things addressed:
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>

> +		#interrupt-cells =3D <2>;
> +		clocks =3D <&cm40_ipg_clk>;
> +		clock-names =3D "ipg";
> +		power-domains =3D <&pd IMX_SC_R_M4_0_INTMUX>;
> +		status =3D "disabled";
> +	};
> +
> +	cm40_i2c_lpcg: clock-controller@37630000 {
> +		compatible =3D "fsl,imx8qxp-lpcg";
> +		reg =3D <0x37630000 0x1000>;
> +		#clock-cells =3D <1>;
> +		clocks =3D <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
> +			 <&cm40_ipg_clk>;
> +		clock-indices =3D <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> +		clock-output-names =3D "cm40_lpcg_i2c_clk",
> +				     "cm40_lpcg_i2c_ipg_clk";
> +		power-domains =3D <&pd IMX_SC_R_M4_0_I2C>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot=
/dts/freescale/imx8dxl.dtsi
> index a0674c5c55766..9d49c75a26222 100644
> --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> @@ -5,6 +5,7 @@
> =20
>  #include <dt-bindings/clock/imx8-clock.h>
>  #include <dt-bindings/dma/fsl-edma.h>
> +#include <dt-bindings/clock/imx8-lpcg.h>
>  #include <dt-bindings/firmware/imx/rsrc.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
>  	};
> =20
>  	/* sorted in register address */
> +	#include "imx8-ss-cm40.dtsi"
>  	#include "imx8-ss-adma.dtsi"
>  	#include "imx8-ss-conn.dtsi"
>  	#include "imx8-ss-ddr.dtsi"
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot=
/dts/freescale/imx8qxp.dtsi
> index 10e16d84c0c3b..0313f295de2e9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -317,6 +317,7 @@ map0 {
>  	/* sorted in register address */
>  	#include "imx8-ss-img.dtsi"
>  	#include "imx8-ss-vpu.dtsi"
> +	#include "imx8-ss-cm40.dtsi"
>  	#include "imx8-ss-gpu0.dtsi"
>  	#include "imx8-ss-adma.dtsi"
>  	#include "imx8-ss-conn.dtsi"
>=20
>=20


=2D-=20
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