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From: Namhyung Kim <namhyung@kernel.org>
To: linux-kernel@vger.kernel.org,
	linux-perf-users@vger.kernel.org,
	Sandipan Das <sandipan.das@amd.com>
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	jolsa@kernel.org,
	ananth.narayan@amd.com,
	acme@kernel.org,
	peterz@infradead.org,
	irogers@google.com,
	alexander.shishkin@linux.intel.com,
	adrian.hunter@intel.com,
	ravi.bangoria@amd.com,
	mark.rutland@arm.com,
	mingo@redhat.com
Subject: Re: [PATCH] perf vendor events amd: Fix Zen 4 cache latency events
Date: Mon,  4 Mar 2024 10:56:44 -0800
Message-ID: <170957856863.1606352.5043156720799964711.b4-ty@kernel.org>
In-Reply-To: <20240301084431.646221-1-sandipan.das@amd.com>
References: <20240301084431.646221-1-sandipan.das@amd.com>
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On Fri, 1 Mar 2024 14:14:31 +0530, Sandipan Das wrote:
> L3PMCx0AC and L3PMCx0AD, used in l3_xi_sampled_latency* events, have a
> quirk that requires them to be programmed with SliceId set to 0x3.
> Without this, the events do not count at all and affects dependent
> metrics such as l3_read_miss_latency.
> 
> If ThreadMask is not specified, the amd-uncore driver internally sets
> ThreadMask to 0x3, EnAllCores to 0x1 and EnAllSlices to 0x1 but does
> not set SliceId. Since SliceId must also be set to 0x3 in this case,
> specify all the other fields explicitly.
> 
> [...]

Applied to perf-tools-next, thanks!

Best regards,
-- 
Namhyung Kim <namhyung@kernel.org>