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From: Gerd Hoffmann <kraxel@redhat.com>
To: kvm@vger.kernel.org
Cc: Tom Lendacky <thomas.lendacky@amd.com>,
	Gerd Hoffmann <kraxel@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>,
	Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)),
	"H. Peter Anvin" <hpa@zytor.com>,
	linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT))
Subject: [PATCH v2] kvm: set guest physical bits in CPUID.0x80000008
Date: Tue,  5 Mar 2024 11:35:06 +0100
Message-ID: <20240305103506.613950-1-kraxel@redhat.com>
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Set CPUID.0x80000008:EAX[23:16] to guest phys bits, i.e. the bits which
are actually addressable.  In most cases this is identical to the host
phys bits, but tdp restrictions (no 5-level paging) can limit this to
48.

Quoting AMD APM (revision 3.35):

  23:16 GuestPhysAddrSize Maximum guest physical address size in bits.
                          This number applies only to guests using nested
                          paging. When this field is zero, refer to the
                          PhysAddrSize field for the maximum guest
                          physical address size. See “Secure Virtual
                          Machine” in APM Volume 2.

Tom Lendacky confirmed the purpose of this field is software use,
hardware always returns zero here.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 arch/x86/kvm/mmu.h     |  2 ++
 arch/x86/kvm/cpuid.c   |  3 ++-
 arch/x86/kvm/mmu/mmu.c | 15 +++++++++++++++
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 60f21bb4c27b..42b5212561c8 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -100,6 +100,8 @@ static inline u8 kvm_get_shadow_phys_bits(void)
 	return boot_cpu_data.x86_phys_bits;
 }
 
+int kvm_mmu_get_guest_phys_bits(void);
+
 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask);
 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index adba49afb5fe..12037f1b017e 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1240,7 +1240,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
 		else if (!g_phys_as)
 			g_phys_as = phys_as;
 
-		entry->eax = g_phys_as | (virt_as << 8);
+		entry->eax = g_phys_as | (virt_as << 8)
+			| kvm_mmu_get_guest_phys_bits() << 16;
 		entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8));
 		entry->edx = 0;
 		cpuid_entry_override(entry, CPUID_8000_0008_EBX);
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 2d6cdeab1f8a..8bebb3e96c8a 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -5267,6 +5267,21 @@ static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
 	return max_tdp_level;
 }
 
+/*
+ * return the actually addressable guest phys bits, which might be
+ * less than host phys bits due to tdp restrictions.
+ */
+int kvm_mmu_get_guest_phys_bits(void)
+{
+	if (tdp_enabled && shadow_phys_bits > 48) {
+		if (tdp_root_level && tdp_root_level != PT64_ROOT_5LEVEL)
+			return 48;
+		if (max_tdp_level != PT64_ROOT_5LEVEL)
+			return 48;
+	}
+	return shadow_phys_bits;
+}
+
 static union kvm_mmu_page_role
 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,
 				union kvm_cpu_role cpu_role)
-- 
2.44.0