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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Tim Pambor <tp@osasysteme.de>, Geert Uytterhoeven
	<geert+renesas@glider.be>
CC: Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley
	<conor+dt@kernel.org>, "linux-renesas-soc@vger.kernel.org"
	<linux-renesas-soc@vger.kernel.org>, "devicetree@vger.kernel.org"
	<devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>
Subject: RE: [PATCH] arm64: dts: r9a07g044: Add complete CPU cache information
Thread-Topic: [PATCH] arm64: dts: r9a07g044: Add complete CPU cache
 information
Thread-Index: AQHabw/kpjnAM2gjZU23vtSxor3NMbEqbAcA
Date: Wed, 6 Mar 2024 09:06:22 +0000
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References: <20240305151336.144707-1-tp@osasysteme.de>
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Hi Tim Pambor,

Thanks for the patch.

> -----Original Message-----
> From: Tim Pambor <tp@osasysteme.de>
> Sent: Tuesday, March 5, 2024 3:14 PM
> Subject: [PATCH] arm64: dts: r9a07g044: Add complete CPU cache informatio=
n
>=20
> Based on ARM Cortex-A55 TRM and RZG2/L user's manual, each Cortex-A55 has

RZ/G2L

> - 32 KB of L1 4-way, set-associative instruction cache
> - 32 KB of L1 4-way, set-associative data cache
>=20
> Each cache has a cache line length of 64B and therefore there are
> 32768B/(4 * 64B)=3D128 sets for each cache.
>=20
> RZG2/L are not configured with the optional per-core L2 cache but only ha=
ve a L3 cache shared among all
RZ/G2L
> cores. In this case, the L3 cache appears as a L2 cache to the system. Th=
erefore, specify "cache-level
> =3D <2>" for the L3 cache.

You mean for L3 Cache, cache-level =3D <2> if there is no L2 Cache on the s=
ystem? Does it need any update
on dt-bindings to make this clear?

Cheers,
Biju

>=20
> Signed-off-by: Tim Pambor <tp@osasysteme.de>
> ---
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
>=20
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot=
/dts/renesas/r9a07g044.dtsi
> index 9f00b75d2bd0..6379c850526a 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -89,6 +89,12 @@ cpu0: cpu@0 {
>  			reg =3D <0>;
>  			device_type =3D "cpu";
>  			#cooling-cells =3D <2>;
> +			d-cache-size =3D <0x8000>;
> +			d-cache-line-size =3D <64>;
> +			d-cache-sets =3D <128>;
> +			i-cache-size =3D <0x8000>;
> +			i-cache-line-size =3D <64>;
> +			i-cache-sets =3D <128>;
>  			next-level-cache =3D <&L3_CA55>;
>  			enable-method =3D "psci";
>  			clocks =3D <&cpg CPG_CORE R9A07G044_CLK_I>; @@ -99,6 +105,12 @@ cpu1:=
 cpu@100 {
>  			compatible =3D "arm,cortex-a55";
>  			reg =3D <0x100>;
>  			device_type =3D "cpu";
> +			d-cache-size =3D <0x8000>;
> +			d-cache-line-size =3D <64>;
> +			d-cache-sets =3D <128>;
> +			i-cache-size =3D <0x8000>;
> +			i-cache-line-size =3D <64>;
> +			i-cache-sets =3D <128>;
>  			next-level-cache =3D <&L3_CA55>;
>  			enable-method =3D "psci";
>  			clocks =3D <&cpg CPG_CORE R9A07G044_CLK_I>; @@ -109,7 +121,7 @@ L3_CA=
55: cache-
> controller-0 {
>  			compatible =3D "cache";
>  			cache-unified;
>  			cache-size =3D <0x40000>;
> -			cache-level =3D <3>;
> +			cache-level =3D <2>;
>  		};
>  	};
>=20
> --
> 2.43.0
>=20