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Date: Wed, 6 Mar 2024 13:11:43 +0000
From: Conor Dooley <conor.dooley@microchip.com>
To: Charlie Jenkins <charlie@rivosinc.com>
CC: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt
	<palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Jisheng Zhang
	<jszhang@kernel.org>, Evan Green <evan@rivosinc.com>,
	=?iso-8859-1?Q?Cl=E9ment_L=E9ger?= <cleger@rivosinc.com>, Eric Biggers
	<ebiggers@kernel.org>, Elliot Berman <quic_eberman@quicinc.com>, Charles Lohr
	<lohr85@gmail.com>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 2/4] riscv: Only check online cpus for emulated
 accesses
Message-ID: <20240306-spry-retread-56d6c8dce327@wendy>
References: <20240301-disable_misaligned_probe_config-v6-0-612ebd69f430@rivosinc.com>
 <20240301-disable_misaligned_probe_config-v6-2-612ebd69f430@rivosinc.com>
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On Fri, Mar 01, 2024 at 05:45:33PM -0800, Charlie Jenkins wrote:
> The unaligned access checker only sets valid values for online cpus.
> Check for these values on online cpus rather than on present cpus.
>=20
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
> Fixes: 71c54b3d169d ("riscv: report misaligned accesses emulation to hwpr=
obe")

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
>  arch/riscv/kernel/traps_misaligned.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra=
ps_misaligned.c
> index 8ded225e8c5b..c2ed4e689bf9 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -632,7 +632,7 @@ void unaligned_emulation_finish(void)
>  	 * accesses emulated since tasks requesting such control can run on any
>  	 * CPU.
>  	 */
> -	for_each_present_cpu(cpu) {
> +	for_each_online_cpu(cpu) {
>  		if (per_cpu(misaligned_access_speed, cpu) !=3D
>  					RISCV_HWPROBE_MISALIGNED_EMULATED) {
>  			return;

I went looking to see what the practical differences were between
"present" and "possible", cos I'd never really seen much code using
"present". Turns out present and possible are essentially the same on
riscv. TIL.

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