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AJvYcCW9F+yxrSFkJAKx1iKM+y2giE0fwSsVNwEtwVLJsMwTZwjn5Uj2Avlq1votCiC6FtstxY1iDepffqHApVBB/AS+CbXK3ZAeYk5gnnukDkSU5pngf6tnisXyMYdr9gbmNeIH6kef8butLoZYcDC7aqlrqWumgjsm7v+12jWZTm/bSdMjkIuvCWM= X-Gm-Message-State: AOJu0YwI5ShLfrBf4Bb6zS4d6nMSplOsGZbJq1FZY9FA1Vqp4r0XVl4c 80ZiUI9Zeg1SzvsXVwIVbp4XXK9VP2nk8Zx4Y8Zj/LVhkdGnKXIt+Zk+PJTMQS8Ye6qHpeEISwb pHbV1YWn4X1PPkbrIBulxLoQHFGW6fVVv X-Received: by 2002:a05:6a20:c222:b0:1a1:42fb:af59 with SMTP id bt34-20020a056a20c22200b001a142fbaf59mr6256789pzb.37.1709797123726; Wed, 06 Mar 2024 23:38:43 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240306123006.724934-1-amadeus@jmu.edu.cn> <20240306123006.724934-2-amadeus@jmu.edu.cn> <78b1a1a2-a9fa-4b28-9d96-d65bb5517199@gmail.com> In-Reply-To: From: Robert Marko Date: Thu, 7 Mar 2024 08:38:32 +0100 Message-ID: Subject: Re: [PATCH v5 1/1] arm64: dts: qcom: ipq6018: add sdhci node To: Dmitry Baryshkov Cc: Chukun Pan , Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Rob Herring , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" On Thu, 7 Mar 2024 at 08:28, Dmitry Baryshkov wrote: > > On Wed, 6 Mar 2024 at 22:35, Robert Marko wrote: > > > > > > On 06. 03. 2024. 20:43, Dmitry Baryshkov wrote: > > > On Wed, 6 Mar 2024 at 14:31, Chukun Pan wrote: > > >> Add node to support mmc controller inside of IPQ6018. > > >> This controller supports both eMMC and SD cards. > > >> > > >> Tested with: > > >> eMMC (HS200) > > >> SD Card (SDR50/SDR104) > > >> > > >> Signed-off-by: Chukun Pan > > >> --- > > >> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++ > > >> 1 file changed, 19 insertions(+) > > >> > > >> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > > >> index 322eced0b876..420c192bccd9 100644 > > >> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi > > >> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi > > >> @@ -441,6 +441,25 @@ dwc_1: usb@7000000 { > > >> }; > > >> }; > > >> > > >> + sdhc: mmc@7804000 { > > >> + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; > > >> + reg = <0x0 0x07804000 0x0 0x1000>, > > >> + <0x0 0x07805000 0x0 0x1000>; > > >> + reg-names = "hc", "cqhci"; > > >> + > > >> + interrupts = , > > >> + ; > > >> + interrupt-names = "hc_irq", "pwr_irq"; > > >> + > > >> + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > > >> + <&gcc GCC_SDCC1_APPS_CLK>, > > >> + <&xo>; > > >> + clock-names = "iface", "core", "xo"; > > >> + resets = <&gcc GCC_SDCC1_BCR>; > > >> + max-frequency = <192000000>; > > > If I understand correctly, GCC_SDCC1_APPS_CLK support frequencies up > > > to 384 MHz, but here you are limiting it to 192 MHz. Why is it so? > > > > > > I am not sure that 384MHz is actually supported as IPQ6018 datasheet > > > clearly indicates that HS400 mode is not supported. > > I didn't check the datasheet, I opened the gcc-ipq6018.c I understand that, I just pointed it out, it wouldn't surprise me if the frequency table was just copy/pasted from IPQ8074. Regards, Robert > > > > > > > Regards, > > > Robert > > > > > >> + status = "disabled"; > > >> + }; > > >> + > > >> blsp_dma: dma-controller@7884000 { > > >> compatible = "qcom,bam-v1.7.0"; > > >> reg = <0x0 0x07884000 0x0 0x2b000>; > > >> -- > > >> 2.25.1 > > >> > > >> > > > > > > > -- > With best wishes > Dmitry