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Date: Thu, 7 Mar 2024 07:54:34 +0000
From: Conor Dooley <conor.dooley@microchip.com>
To: Charlie Jenkins <charlie@rivosinc.com>
CC: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt
	<palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Jisheng Zhang
	<jszhang@kernel.org>, Evan Green <evan@rivosinc.com>,
	=?iso-8859-1?Q?Cl=E9ment_L=E9ger?= <cleger@rivosinc.com>, Eric Biggers
	<ebiggers@kernel.org>, Elliot Berman <quic_eberman@quicinc.com>, Charles Lohr
	<lohr85@gmail.com>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v7 3/4] riscv: Decouple emulated unaligned accesses from
 access speed
Message-ID: <20240307-during-unlovely-d5c3cd6dc4a6@wendy>
References: <20240306-disable_misaligned_probe_config-v7-0-6c90419e7a96@rivosinc.com>
 <20240306-disable_misaligned_probe_config-v7-3-6c90419e7a96@rivosinc.com>
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In-Reply-To: <20240306-disable_misaligned_probe_config-v7-3-6c90419e7a96@rivosinc.com>

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On Wed, Mar 06, 2024 at 12:00:03PM -0800, Charlie Jenkins wrote:
> Detecting if a system traps into the kernel on an unaligned access
> can be performed separately from checking the speed of unaligned
> accesses. This decoupling will make it possible to selectively enable
> or disable each of these checks

> as is done in the following patch.

nit: these sort of comments can bitrot if things get backported or
may not be accurate if only partial series get applied to a branch.

> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
>  arch/riscv/include/asm/cpufeature.h  |  2 +-
>  arch/riscv/kernel/cpufeature.c       | 25 +++++++++++++++++++++----
>  arch/riscv/kernel/traps_misaligned.c | 15 +++++++--------
>  3 files changed, 29 insertions(+), 13 deletions(-)
>=20
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm=
/cpufeature.h
> index 466e1f591919..6fec91845aa0 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -37,7 +37,7 @@ void riscv_user_isa_enable(void);
> =20
>  #ifdef CONFIG_RISCV_MISALIGNED
>  bool unaligned_ctl_available(void);
> -bool check_unaligned_access_emulated(int cpu);
> +bool check_unaligned_access_emulated_all_cpus(void);
>  void unaligned_emulation_finish(void);
>  #else
>  static inline bool unaligned_ctl_available(void)
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeatur=
e.c
> index 7878cddccc0d..abb3a2f53106 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -719,7 +719,8 @@ static int check_unaligned_access(void *param)
>  	void *src;
>  	long speed =3D RISCV_HWPROBE_MISALIGNED_SLOW;
> =20
> -	if (check_unaligned_access_emulated(cpu))
> +	if (IS_ENABLED(CONFIG_RISCV_MISALIGNED) &&
> +	    per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISALIGNED=
_UNKNOWN)
>  		return 0;
> =20
>  	/* Make an unaligned destination buffer. */
> @@ -896,8 +897,8 @@ static int riscv_offline_cpu(unsigned int cpu)
>  	return 0;
>  }
> =20
> -/* Measure unaligned access on all CPUs present at boot in parallel. */
> -static int check_unaligned_access_all_cpus(void)
> +/* Measure unaligned access speed on all CPUs present at boot in paralle=
l. */
> +static int check_unaligned_access_speed_all_cpus(void)
>  {
>  	unsigned int cpu;
>  	unsigned int cpu_count =3D num_possible_cpus();
> @@ -935,7 +936,6 @@ static int check_unaligned_access_all_cpus(void)
>  				  riscv_online_cpu, riscv_offline_cpu);
> =20
>  out:
> -	unaligned_emulation_finish();
>  	for_each_cpu(cpu, cpu_online_mask) {
>  		if (bufs[cpu])
>  			__free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER);
> @@ -945,6 +945,23 @@ static int check_unaligned_access_all_cpus(void)
>  	return 0;
>  }
> =20
> +#ifdef CONFIG_RISCV_MISALIGNED
> +static int check_unaligned_access_all_cpus(void)
> +{
> +	bool all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus();
> +
> +	if (!all_cpus_emulated)
> +		return check_unaligned_access_speed_all_cpus();
> +
> +	return 0;
> +}
> +#else
> +static int check_unaligned_access_all_cpus(void)
> +{
> +	return check_unaligned_access_speed_all_cpus();
> +}
> +#endif
> +
>  arch_initcall(check_unaligned_access_all_cpus);
> =20
>  void riscv_user_isa_enable(void)
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra=
ps_misaligned.c
> index c2ed4e689bf9..e55718179f42 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -596,7 +596,7 @@ int handle_misaligned_store(struct pt_regs *regs)
>  	return 0;
>  }
> =20
> -bool check_unaligned_access_emulated(int cpu)
> +static bool check_unaligned_access_emulated(int cpu)
>  {
>  	long *mas_ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu);
>  	unsigned long tmp_var, tmp_val;
> @@ -623,7 +623,7 @@ bool check_unaligned_access_emulated(int cpu)
>  	return misaligned_emu_detected;
>  }
> =20
> -void unaligned_emulation_finish(void)
> +bool check_unaligned_access_emulated_all_cpus(void)
>  {
>  	int cpu;
> =20
> @@ -632,13 +632,12 @@ void unaligned_emulation_finish(void)
>  	 * accesses emulated since tasks requesting such control can run on any
>  	 * CPU.
>  	 */
> -	for_each_online_cpu(cpu) {
> -		if (per_cpu(misaligned_access_speed, cpu) !=3D
> -					RISCV_HWPROBE_MISALIGNED_EMULATED) {
> -			return;
> -		}
> -	}
> +	for_each_online_cpu(cpu)
> +		if (!check_unaligned_access_emulated(cpu))
> +			return false;
> +
>  	unaligned_ctl =3D true;
> +	return true;
>  }
> =20
>  bool unaligned_ctl_available(void)
>=20
> --=20
> 2.43.2
>=20

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