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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL1PR11MB5271.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 50a8e5d0-73b6-4dd5-c680-08dc3e809aab X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Mar 2024 08:28:45.0978 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: gMOUN8qKGXnmh41LW0MyFxl6i2ZdcmfF//Pz6XHcUVwnTQq/iHzbzyB/dSDWllobdccW5yBzXsdo+6655qsDzg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB6095 X-OriginatorOrg: intel.com > From: Alex Williamson > Sent: Thursday, March 7, 2024 5:15 AM >=20 > Currently for devices requiring masking at the irqchip for INTx, ie. > devices without DisINTx support, the IRQ is enabled in request_irq() > and subsequently disabled as necessary to align with the masked status > flag. This presents a window where the interrupt could fire between > these events, resulting in the IRQ incrementing the disable depth twice. Can you elaborate the last point about disable depth? > This would be unrecoverable for a user since the masked flag prevents > nested enables through vfio. What is 'nested enables'? >=20 > Instead, invert the logic using IRQF_NO_AUTOEN such that exclusive INTx > is never auto-enabled, then unmask as required. >=20 > Fixes: 89e1f7d4c66d ("vfio: Add PCI device driver") > Signed-off-by: Alex Williamson But this patch looks good to me: Reviewed-by: Kevin Tian with one nit... >=20 > + /* > + * Devices without DisINTx support require an exclusive interrupt, > + * IRQ masking is performed at the IRQ chip. The masked status is "exclusive interrupt, with IRQ masking performed at..."