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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Thu, 7 Mar 2024 10:08:43 +0000
Message-ID: <CA+V-a8vunmsUfGkFO30nwvqFkiks7vceLgG1jo7TcsFajeckmQ@mail.gmail.com>
Subject: Re: [PATCH] dt-bindings: serial: renesas,scif: Document R9A09G057 support
To: Geert Uytterhoeven <geert@linux-m68k.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>, 
	Rob Herring <robh+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Magnus Damm <magnus.damm@gmail.com>, linux-kernel@vger.kernel.org, 
	linux-serial@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-renesas-soc@vger.kernel.org, 
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Geert,

On Wed, Mar 6, 2024 at 10:21=E2=80=AFAM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Geert,
>
> On Wed, Mar 6, 2024 at 10:15=E2=80=AFAM Geert Uytterhoeven <geert@linux-m=
68k.org> wrote:
> >
> > Hi Prabhakar,
> >
> > On Wed, Mar 6, 2024 at 11:06=E2=80=AFAM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Wed, Mar 6, 2024 at 9:53=E2=80=AFAM Geert Uytterhoeven <geert@linu=
x-m68k.org> wrote:
> > > > On Tue, Mar 5, 2024 at 6:16=E2=80=AFPM Prabhakar <prabhakar.csengg@=
gmail.com> wrote:
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Document support for the Serial Communication Interface with FIFO=
 (SCIF)
> > > > > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF inte=
rface in
> > > > > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L
> > > > > (R9A07G044) SoC, with the only difference being that the RZ/V2H(P=
) SoC has
> > > > > three additional interrupts: one for Tx end/Rx ready and the othe=
r two for
> > > > > Rx and Tx buffer full, which are edge-triggered.
> > > > >
> > > > > No driver changes are required as generic compatible string
> > > > > "renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) =
SoC.
> > > >
> > > > If you declare SCIF on RZ/V2H compatible with SCIF on RZ/G2L, you
> > > > state that the current driver works fine (but perhaps suboptimal),
> > > > without adding support for the extra 3 interrupts?
> > > >
> > > Yes the current driver works without using the extra interrupts on th=
e
> > > RZ/V2H. The extra interrupts on the RZ/V2H are just sort of duplicate
> > > ie
> > > - Transmit End/Data Ready interrupt , for which we we have two
> > > seperate interrupts already
> > > - Receive buffer full interrupt (EDGE trigger), for which we already
> > > have a Level triggered interrupt
> > > - Transmit buffer empty interrupt (EDGE trigger), for which we alread=
y
> > > have a Level triggered interrupt
> >
> > Thanks for the confirmation!
> >
> > > Are you suggesting to not fallback on RZ/G2L and instead make RZ/V2H
> > > an explicit one so that in future we handle these 3 extra interrupts?
> >
> > In light of the confirmation above, I am _not_ suggesting that.
> >
With the introduction of validation checks for interrupts, falling
back to "renesas,scif-r9a07g044" for RZ/V2H will be difficult for
validating interrupt count.

  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,scif-r7s9210
              - renesas,scif-r9a07g044
    then:
      properties:
        interrupts:
          minItems: 6

        interrupt-names:
          minItems: 6

With the above check RZ/V2H fall into this if block,

Is there any way I can specify to match two compat strings?

Cheers,
Prabhakar