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In-Reply-To: <871q8mdr2i.fsf@all.your.base.are.belong.to.us>
From: Anup Patel <apatel@ventanamicro.com>
Date: Thu, 7 Mar 2024 20:55:21 +0530
Message-ID: <CAK9=C2UfpTtQ6DOSE7-EVsC+zyYAY6CvigQ6iDLuLgQNj2e5vw@mail.gmail.com>
Subject: Re: [PATCH v15 08/10] irqchip/riscv-aplic: Add support for MSI-mode
To: =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, 
	Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Frank Rowand <frowand.list@gmail.com>, 
	Conor Dooley <conor+dt@kernel.org>, devicetree@vger.kernel.org, 
	Saravana Kannan <saravanak@google.com>, Marc Zyngier <maz@kernel.org>, Anup Patel <anup@brainfault.org>, 
	linux-kernel@vger.kernel.org, Atish Patra <atishp@atishpatra.org>, 
	linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, 
	Andrew Jones <ajones@ventanamicro.com>
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On Thu, Mar 7, 2024 at 8:31=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel <bjorn@kernel.=
org> wrote:
>
> Anup Patel <apatel@ventanamicro.com> writes:
>
> > On Wed, Mar 6, 2024 at 9:22=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel <bjorn@ker=
nel.org> wrote:
> >>
> >> Anup Patel <apatel@ventanamicro.com> writes:
> >>
> >> > diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip=
/irq-riscv-aplic-msi.c
> >> > new file mode 100644
> >> > index 000000000000..b2a25e011bb2
> >> > --- /dev/null
> >> > +++ b/drivers/irqchip/irq-riscv-aplic-msi.c
> >> > +static void aplic_msi_write_msg(struct irq_data *d, struct msi_msg =
*msg)
> >> > +{
> >> > +     unsigned int group_index, hart_index, guest_index, val;
> >> > +     struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d);
> >> > +     struct aplic_msicfg *mc =3D &priv->msicfg;
> >> > +     phys_addr_t tppn, tbppn, msg_addr;
> >> > +     void __iomem *target;
> >> > +
> >> > +     /* For zeroed MSI, simply write zero into the target register =
*/
> >> > +     if (!msg->address_hi && !msg->address_lo && !msg->data) {
> >> > +             target =3D priv->regs + APLIC_TARGET_BASE;
> >> > +             target +=3D (d->hwirq - 1) * sizeof(u32);
> >> > +             writel(0, target);
> >>
> >> Is the fence needed here (writel_relaxed())...
> >
> > The pci_write_msg_msix() (called via pci_msi_domain_write_msg())
> > uses writel() hence taking inspiration from that we use writel() over h=
ere
> > as well.
> >
> > If that's wrong then pci_write_msg_msix() must be fixed as well.
>
> Huh? The writel()s in pci_write_msg_msix() are because there's an
> ordering constraint, and code would be broken w/o it. My question was
> "what are the ordering constraints for this piece of code", because it
> looks like this is a single I/O write without any ordering constraints.

Whatever ordering constraints apply to pci_write_msg_msix() also
apply to APLIC MSI-mode because both create the leaf-level IRQ
domain for the client device driver (PCIe or Platform device) whose
parent is IMSIC base domain.

>
> I'm not a fan of sprinkling fences around "to be safe", but I don't want
> to delay the v16 because of it. It can be fixed later, if it's not
> needed.

I don't think there is a clear way of proving that using write_relaxed()
in aplic_msi_write_msg() is safe considering there is a vast variety
of platform drivers who would be clients of the APLIC MSI-mode
domain.

I agree that we should deal with this later.

Regards,
Anup