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From: =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley
 <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Rob
 Herring <robh+dt@kernel.org>, Krzysztof Kozlowski
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 Zyngier <maz@kernel.org>, Anup Patel <anup@brainfault.org>,
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 linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org,
 Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH v15 08/10] irqchip/riscv-aplic: Add support for MSI-mode
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 <87y1avbboj.fsf@all.your.base.are.belong.to.us>
 <CAK9=C2Ud+CJzWfY0Lp97OMt9QvJBFX=hHJidn_90XY5cEB9LHw@mail.gmail.com>
Date: Thu, 07 Mar 2024 16:01:09 +0100
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Anup Patel <apatel@ventanamicro.com> writes:

> On Wed, Mar 6, 2024 at 9:22=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel <bjorn@kerne=
l.org> wrote:
>>
>> Anup Patel <apatel@ventanamicro.com> writes:
>>
>> > diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/i=
rq-riscv-aplic-msi.c
>> > new file mode 100644
>> > index 000000000000..b2a25e011bb2
>> > --- /dev/null
>> > +++ b/drivers/irqchip/irq-riscv-aplic-msi.c
>> > +static void aplic_msi_write_msg(struct irq_data *d, struct msi_msg *m=
sg)
>> > +{
>> > +     unsigned int group_index, hart_index, guest_index, val;
>> > +     struct aplic_priv *priv =3D irq_data_get_irq_chip_data(d);
>> > +     struct aplic_msicfg *mc =3D &priv->msicfg;
>> > +     phys_addr_t tppn, tbppn, msg_addr;
>> > +     void __iomem *target;
>> > +
>> > +     /* For zeroed MSI, simply write zero into the target register */
>> > +     if (!msg->address_hi && !msg->address_lo && !msg->data) {
>> > +             target =3D priv->regs + APLIC_TARGET_BASE;
>> > +             target +=3D (d->hwirq - 1) * sizeof(u32);
>> > +             writel(0, target);
>>
>> Is the fence needed here (writel_relaxed())...
>
> The pci_write_msg_msix() (called via pci_msi_domain_write_msg())
> uses writel() hence taking inspiration from that we use writel() over here
> as well.
>
> If that's wrong then pci_write_msg_msix() must be fixed as well.

Huh? The writel()s in pci_write_msg_msix() are because there's an
ordering constraint, and code would be broken w/o it. My question was
"what are the ordering constraints for this piece of code", because it
looks like this is a single I/O write without any ordering constraints.

I'm not a fan of sprinkling fences around "to be safe", but I don't want
to delay the v16 because of it. It can be fixed later, if it's not
needed.


Cheers, and thanks for your hard work!
Bj=C3=B6rn