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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Date: Thu, 7 Mar 2024 17:36:51 +0100
Message-ID: <CAMhs-H_eUKm7C40oCzuKwwEMZAcOJ-g4MghAfkGAmxRM0AXPUw@mail.gmail.com>
Subject: Re: [PATCH 2/2] mips: dts: ralink: mt7621: add serial1 and serial2 nodes
To: Justin Swartz <justin.swartz@risingedge.co.za>
Cc: =?UTF-8?B?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>, 
	Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>, Matthias Brugger <matthias.bgg@gmail.com>, 
	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, linux-mips@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
	linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org
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Hi Justin,

On Thu, Mar 7, 2024 at 4:15=E2=80=AFPM Justin Swartz
<justin.swartz@risingedge.co.za> wrote:
>
> Hi Sergio
>
> On 2024-03-07 12:04, Sergio Paracuellos wrote:
> > Hi Justin,
> >
> > On Wed, Mar 6, 2024 at 9:11=E2=80=AFPM Justin Swartz
> > <justin.swartz@risingedge.co.za> wrote:
> >>
> >> Add serial1 and serial2 nodes to define the existence of
> >> UART1 and UART2.
> >>
> >> Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
> >> ---
> >>  arch/mips/boot/dts/ralink/mt7621.dtsi | 38
> >> +++++++++++++++++++++++++++
> >>  1 file changed, 38 insertions(+)
> >>
> >> diff --git a/arch/mips/boot/dts/ralink/mt7621.dtsi
> >> b/arch/mips/boot/dts/ralink/mt7621.dtsi
> >> index dca415fdd..2069249c8 100644
> >> --- a/arch/mips/boot/dts/ralink/mt7621.dtsi
> >> +++ b/arch/mips/boot/dts/ralink/mt7621.dtsi
> >> @@ -128,6 +128,44 @@ serial0: serial@c00 {
> >>                         pinctrl-0 =3D <&uart1_pins>;
> >>                 };
> >>
> >> +               serial1: serial@d00 {
> >> +                       status =3D "disabled";
> >> +
> >> +                       compatible =3D "ns16550a";
> >> +                       reg =3D <0xd00 0x100>;
> >> +
> >> +                       clocks =3D <&sysc MT7621_CLK_UART2>;
> >> +
> >> +                       interrupt-parent =3D <&gic>;
> >> +                       interrupts =3D <GIC_SHARED 27
> >> IRQ_TYPE_LEVEL_HIGH>;
> >> +
> >> +                       reg-shift =3D <2>;
> >> +                       reg-io-width =3D <4>;
> >> +                       no-loopback-test;
> >> +
> >> +                       pinctrl-names =3D "default";
> >> +                       pinctrl-0 =3D <&uart2_pins>;
> >> +               };
> >> +
> >> +               serial2: serial@e00 {
> >> +                       status =3D "disabled";
> >> +
> >> +                       compatible =3D "ns16550a";
> >> +                       reg =3D <0xe00 0x100>;
> >> +
> >> +                       clocks =3D <&sysc MT7621_CLK_UART3>;
> >> +
> >> +                       interrupt-parent =3D <&gic>;
> >> +                       interrupts =3D <GIC_SHARED 28
> >> IRQ_TYPE_LEVEL_HIGH>;
> >> +
> >> +                       reg-shift =3D <2>;
> >> +                       reg-io-width =3D <4>;
> >> +                       no-loopback-test;
> >> +
> >> +                       pinctrl-names =3D "default";
> >> +                       pinctrl-0 =3D <&uart3_pins>;
> >> +               };
> >> +
> >
> > Please follow the preferred order for properties described in dts
> > coding style [0]. I know that there is some mess around the properties
> > order in some nodes with the current dtsi file but we did not have
> > coding style before and now we have it, so I think we should follow it
> > at least for new additions.
>
> No problem. I see you've already "Acked-by" patch 1 (adding pinctrl
> properties to serial0) of this set, so would it be a better move to
> submit a new patch set that would look something like:
>
>   1. add pinctrl-name and pinctrl-0 to serial0 [no changes from what I
> sent]
>   2. reorder serial0 properties according to the DTS style guidelines
>   3. add serial1 and serial2 with the correct property order

This would be ok, thank you.

Best regards,
    Sergio Paracuellos