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Fri, 8 Mar 2024 03:09:02 GMT Received: from [10.216.20.61] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 7 Mar 2024 19:08:56 -0800 Message-ID: Date: Fri, 8 Mar 2024 08:38:52 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: [PATCH v2] PCI: dwc: Enable runtime pm of the host bridge Content-Language: en-US To: Bjorn Helgaas , "Rafael J. Wysocki" CC: Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Rob Herring , Bjorn Helgaas , , , , , , , References: <20240307215505.GA632869@bhelgaas> From: Krishna Chaitanya Chundru In-Reply-To: <20240307215505.GA632869@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Zr3Z94GuKV4sm2K3ytlSAPueUTSiyLlz X-Proofpoint-GUID: Zr3Z94GuKV4sm2K3ytlSAPueUTSiyLlz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-08_02,2024-03-06_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 bulkscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403080024 On 3/8/2024 3:25 AM, Bjorn Helgaas wrote: > [+to Rafael, sorry, another runtime PM question, beginning of thread: > https://lore.kernel.org/r/20240305-runtime_pm_enable-v2-1-a849b74091d1@quicinc.com] > > On Thu, Mar 07, 2024 at 07:28:54AM +0530, Krishna Chaitanya Chundru wrote: >> On 3/6/2024 1:27 AM, Bjorn Helgaas wrote: >>> On Tue, Mar 05, 2024 at 03:19:01PM +0530, Krishna chaitanya chundru wrote: >>>> The Controller driver is the parent device of the PCIe host bridge, >>>> PCI-PCI bridge and PCIe endpoint as shown below. >>>> >>>> PCIe controller(Top level parent & parent of host bridge) >>>> | >>>> v >>>> PCIe Host bridge(Parent of PCI-PCI bridge) >>>> | >>>> v >>>> PCI-PCI bridge(Parent of endpoint driver) >>>> | >>>> v >>>> PCIe endpoint driver >>>> >>>> Since runtime PM is disabled for host bridge, the state of the child >>>> devices under the host bridge is not taken into account by PM framework >>>> for the top level parent, PCIe controller. So PM framework, allows >>>> the controller driver to enter runtime PM irrespective of the state >>>> of the devices under the host bridge. >>> >>> IIUC this says that we runtime suspend the controller even though >>> runtime PM is disabled for the host bridge? I have a hard time >>> parsing this; can you cite a function that does this or some relevant >>> documentation about how this part of runtime PM works? >>> >> Generally controller should go to runtime suspend when endpoint client >> drivers and pci-pci host bridge drivers goes to runtime suspend as the >> controller driver is the parent, but we are observing controller driver >> goes to runtime suspend even when client drivers and PCI-PCI bridge are >> in active state. > > It surprises me that a device could be suspended while children are > active. A PCI-PCI bridge must be in D0 for any devices below it to be > active. The controller is a platform device, not a PCI device, but I > am similarly surprised that we would suspend it when children are > active, which makes me think we didn't set the hierarchy up correctly. > > It doesn't seem like we should need to enable runtime PM for a parent > to keep it from being suspended when children are active. Here we are not enabling runtime PM of the controller device, we are enabling runtime PM for the bridge device which is maintained by the PCIe framework. The bridge device is the parent of the PCI-PCI bridge and child of the controller device. As the bridge device's runtime PM is not enabled the PM framework is ignoring the child's runtime status. - Krishna Chaitanya. >>>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >>>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >>>> @@ -16,6 +16,7 @@ >>>> #include >>>> #include >>>> #include >>>> +#include >>>> >>>> #include "../../pci.h" >>>> #include "pcie-designware.h" >>>> @@ -505,6 +506,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) >>>> if (pp->ops->post_init) >>>> pp->ops->post_init(pp); >>>> >>>> + pm_runtime_set_active(&bridge->dev); >>>> + pm_runtime_enable(&bridge->dev); >>>> + >>>> return 0; >>>> >>>> err_stop_link: > > Bjorn