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b=JbTslvAkKWoXbwAMowf8jC5CKpV8emgYuJxAc7noBOCGsihi0I7Ko05/ilQtrylssYTd2FON6jjj04ZHqRe9PkLrxM7IPzfgX6osOHmcqVfJEE5fgAb7zLylk9vhrz5C+HWN8D9CduCXpOqFrTVwRNh7xuOpNpXzTeawWLOEbmY= Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by DU2PR04MB8552.eurprd04.prod.outlook.com (2603:10a6:10:2d7::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Fri, 8 Mar 2024 03:36:05 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7339.035; Fri, 8 Mar 2024 03:36:05 +0000 From: Xu Yang To: Frank Li CC: "will@kernel.org" , "mark.rutland@arm.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , "festevam@gmail.com" , "john.g.garry@oracle.com" , "jolsa@kernel.org" , "namhyung@kernel.org" , "irogers@google.com" , "mike.leach@linaro.org" , "peterz@infradead.org" , "mingo@redhat.com" , "acme@kernel.org" , "alexander.shishkin@linux.intel.com" , "adrian.hunter@intel.com" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-perf-users@vger.kernel.org" , "imx@lists.linux.dev" Subject: RE: [PATCH v6 2/7] perf: imx_perf: add macro definitions for parsing config attr Thread-Topic: [PATCH v6 2/7] perf: imx_perf: add macro definitions for parsing config attr Thread-Index: AQHacHXeU0pTCoFFP0+C3lSU2gJvhbEse/UAgAC2VxA= Date: Fri, 8 Mar 2024 03:36:05 +0000 Message-ID: References: <20240307095730.3792680-1-xu.yang_2@nxp.com> <20240307095730.3792680-2-xu.yang_2@nxp.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8822.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c6014148-4fd4-4431-c004-08dc3f20e279 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Mar 2024 03:36:05.0458 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7cLuolk6gPVxe//6BXHBdbM6lQ3h38ZVtroim8GNrHUvuQpndz+fIhr65rYdmhWxOtLG774UhvT8sOSxGtFbeQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8552 >=20 > On Thu, Mar 07, 2024 at 05:57:25PM +0800, Xu Yang wrote: > > The user can set event and counter in cmdline and the driver need to pa= rse > > it using 'config' attr value. This will add macro definitions to avoid > > hard-code in driver. > > > > Signed-off-by: Xu Yang > > > > --- > > Changes in v4: > > - new patch > > Changes in v5: > > - move this patch earlier > > Changes in v6: > > - no changes > > --- > > drivers/perf/fsl_imx9_ddr_perf.c | 15 +++++++++++---- > > 1 file changed, 11 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_d= dr_perf.c > > index 9685645bfe04..d1c566e661d8 100644 > > --- a/drivers/perf/fsl_imx9_ddr_perf.c > > +++ b/drivers/perf/fsl_imx9_ddr_perf.c > > @@ -42,6 +42,11 @@ > > #define NUM_COUNTERS 11 > > #define CYCLES_COUNTER 0 > > > > +#define CONFIG_EVENT_MASK 0x00FF > > +#define CONFIG_EVENT_OFFSET 0 >=20 > Needn't need OFFSET if use FIELD_* Okay, I will use FIELD_*. >=20 > > +#define CONFIG_COUNTER_MASK 0xFF00 > > +#define CONFIG_COUNTER_OFFSET 8 >=20 > The same >=20 > > + > > #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) > > > > #define DDR_PERF_DEV_NAME "imx9_ddr" > > @@ -339,8 +344,10 @@ static void ddr_perf_counter_local_config(struct d= dr_pmu *pmu, int config, > > int counter, bool enable) > > { > > u32 ctrl_a; > > + int event; > > > > ctrl_a =3D readl_relaxed(pmu->base + PMLCA(counter)); > > + event =3D (config & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; >=20 > FIELD_GET(CONFIG_EVENT_MASK, config); >=20 > same below all code about config. Okay. Thanks, Xu Yang >=20 > > > > if (enable) { > > ctrl_a |=3D PMLCA_FC; > > @@ -352,7 +359,7 @@ static void ddr_perf_counter_local_config(struct dd= r_pmu *pmu, int config, > > ctrl_a &=3D ~PMLCA_FC; > > ctrl_a |=3D PMLCA_CE; > > ctrl_a &=3D ~FIELD_PREP(PMLCA_EVENT, 0x7F); > > - ctrl_a |=3D FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF)); > > + ctrl_a |=3D FIELD_PREP(PMLCA_EVENT, event); > > writel(ctrl_a, pmu->base + PMLCA(counter)); > > } else { > > /* Freeze counter. */ > > @@ -366,8 +373,8 @@ static void ddr_perf_monitor_config(struct ddr_pmu = *pmu, int cfg, int cfg1, int > > u32 pmcfg1, pmcfg2; > > int event, counter; > > > > - event =3D cfg & 0x000000FF; > > - counter =3D (cfg & 0x0000FF00) >> 8; > > + event =3D (cfg & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; > > + counter =3D (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; > > > > pmcfg1 =3D readl_relaxed(pmu->base + PMCFG1); > > > > @@ -469,7 +476,7 @@ static int ddr_perf_event_add(struct perf_event *ev= ent, int flags) > > int cfg2 =3D event->attr.config2; > > int counter; > > > > - counter =3D (cfg & 0x0000FF00) >> 8; > > + counter =3D (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; > > > > pmu->events[counter] =3D event; > > pmu->active_events++; > > -- > > 2.34.1 > >