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From: Xu Yang <xu.yang_2@nxp.com>
To: Frank Li <frank.li@nxp.com>
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Subject: RE: [PATCH v6 4/7] perf: imx_perf: refactor driver for imx93
Thread-Topic: [PATCH v6 4/7] perf: imx_perf: refactor driver for imx93
Thread-Index: AQHacHXnJDlhKGFOKEyD8xAIge0Eu7Esf7qAgAD0xrA=
Date: Fri, 8 Mar 2024 07:32:57 +0000
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References: <20240307095730.3792680-1-xu.yang_2@nxp.com>
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>=20
> On Thu, Mar 07, 2024 at 05:57:27PM +0800, Xu Yang wrote:
> > This driver is initinally used to support imx93 Soc and now it's time t=
o
> > add support for imx95 Soc. However, some macro definitions and events a=
re
> > different on these two Socs. For preparing imx95 supports, this will
> > refactor driver for imx93.
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> >
> > ---
> > Changes in v4:
> >  - new patch
> > Changes in v5:
> >  - use is_visible to hide unwanted attributes as suggested by Will
> > Changes in v6:
> >  - improve imx93_ddr_perf_monitor_config()
> > ---
> >  drivers/perf/fsl_imx9_ddr_perf.c | 99 +++++++++++++++++++++-----------
> >  1 file changed, 66 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_d=
dr_perf.c
> > index 8d85b4d98544..4e8a3a4349c5 100644
> > --- a/drivers/perf/fsl_imx9_ddr_perf.c
> > +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> > @@ -11,14 +11,14 @@
> >  #include <linux/perf_event.h>
> >
> >  /* Performance monitor configuration */
> > -#define PMCFG1  			0x00
> > -#define PMCFG1_RD_TRANS_FILT_EN 	BIT(31)
> > -#define PMCFG1_WR_TRANS_FILT_EN 	BIT(30)
> > -#define PMCFG1_RD_BT_FILT_EN 		BIT(29)
> > -#define PMCFG1_ID_MASK  		GENMASK(17, 0)
> > +#define PMCFG1				0x00
> > +#define MX93_PMCFG1_RD_TRANS_FILT_EN	BIT(31)
> > +#define MX93_PMCFG1_WR_TRANS_FILT_EN	BIT(30)
> > +#define MX93_PMCFG1_RD_BT_FILT_EN	BIT(29)
> > +#define MX93_PMCFG1_ID_MASK		GENMASK(17, 0)
> >
> > -#define PMCFG2  			0x04
> > -#define PMCFG2_ID			GENMASK(17, 0)
> > +#define PMCFG2				0x04
> > +#define MX93_PMCFG2_ID			GENMASK(17, 0)
> >
> >  /* Global control register affects all counters and takes priority ove=
r local control registers */
> >  #define PMGC0		0x40
> > @@ -77,6 +77,11 @@ static const struct imx_ddr_devtype_data imx93_devty=
pe_data =3D {
> >  	.identifier =3D "imx93",
> >  };
> >
> > +static inline bool is_imx93(struct ddr_pmu *pmu)
> > +{
> > +	return pmu->devtype_data =3D=3D &imx93_devtype_data;
> > +}
> > +
> >  static const struct of_device_id imx_ddr_pmu_dt_ids[] =3D {
> >  	{.compatible =3D "fsl,imx93-ddr-pmu", .data =3D &imx93_devtype_data},
> >  	{ /* sentinel */ }
> > @@ -186,7 +191,7 @@ static struct attribute *ddr_perf_events_attrs[] =
=3D {
> >  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)),
> >  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)),
> >  	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)),
> > -	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)),
> > +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)),	/* imx93=
 specific*/
> >
> >  	/* counter3 specific events */
> >  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)),
> > @@ -198,7 +203,7 @@ static struct attribute *ddr_perf_events_attrs[] =
=3D {
> >  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)),
> >  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)),
> >  	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)),
> > -	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)),
> > +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)),	/* imx93=
 specific*/
> >
> >  	/* counter4 specific events */
> >  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)),
> > @@ -210,7 +215,7 @@ static struct attribute *ddr_perf_events_attrs[] =
=3D {
> >  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)),
> >  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)),
> >  	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)),
> > -	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)),
> > +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)),	/* imx93 =
specific*/
> >
> >  	/* counter5 specific events */
> >  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)),
> > @@ -245,9 +250,26 @@ static struct attribute *ddr_perf_events_attrs[] =
=3D {
> >  	NULL,
> >  };
> >
> > +static umode_t
> > +ddr_perf_events_attrs_is_visible(struct kobject *kobj,
> > +				       struct attribute *attr, int unused)
> > +{
> > +	struct pmu *pmu =3D dev_get_drvdata(kobj_to_dev(kobj));
> > +	struct ddr_pmu *ddr_pmu =3D to_ddr_pmu(pmu);
> > +
> > +	if ((!strcmp(attr->name, "eddrtq_pm_rd_trans_filt") ||
> > +		!strcmp(attr->name, "eddrtq_pm_wr_trans_filt") ||
> > +		!strcmp(attr->name, "eddrtq_pm_rd_beat_filt")) &&
> > +		!is_imx93(ddr_pmu))
> > +		return 0;
> > +
> > +	return attr->mode;
> > +}
> > +
> >  static const struct attribute_group ddr_perf_events_attr_group =3D {
> >  	.name =3D "events",
> >  	.attrs =3D ddr_perf_events_attrs,
> > +	.is_visible =3D ddr_perf_events_attrs_is_visible,
> >  };
> >
> >  PMU_FORMAT_ATTR(event, "config:0-15");
> > @@ -369,36 +391,47 @@ static void ddr_perf_counter_local_config(struct =
ddr_pmu *pmu, int config,
> >  	}
> >  }
> >
> > -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int event,
> > -				    int counter, int axi_id, int axi_mask)
> > +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int eve=
nt,
> > +					  int counter, int axi_id, int axi_mask)
> >  {
> >  	u32 pmcfg1, pmcfg2;
> >
> >  	pmcfg1 =3D readl_relaxed(pmu->base + PMCFG1);
> >
> > -	if (counter =3D=3D 2 && event =3D=3D 73)
> > -		pmcfg1 |=3D PMCFG1_RD_TRANS_FILT_EN;
> > -	else if (counter =3D=3D 2 && event !=3D 73)
> > -		pmcfg1 &=3D ~PMCFG1_RD_TRANS_FILT_EN;
> > -
> > -	if (counter =3D=3D 3 && event =3D=3D 73)
> > -		pmcfg1 |=3D PMCFG1_WR_TRANS_FILT_EN;
> > -	else if (counter =3D=3D 3 && event !=3D 73)
> > -		pmcfg1 &=3D ~PMCFG1_WR_TRANS_FILT_EN;
> > -
> > -	if (counter =3D=3D 4 && event =3D=3D 73)
> > -		pmcfg1 |=3D PMCFG1_RD_BT_FILT_EN;
> > -	else if (counter =3D=3D 4 && event !=3D 73)
> > -		pmcfg1 &=3D ~PMCFG1_RD_BT_FILT_EN;
> > +	if (event =3D=3D 73) {
> > +		switch (counter) {
> > +		case 2:
> > +			pmcfg1 |=3D MX93_PMCFG1_RD_TRANS_FILT_EN;
> > +			break;
> > +		case 3:
> > +			pmcfg1 |=3D MX93_PMCFG1_WR_TRANS_FILT_EN;
> > +			break;
> > +		case 4:
> > +			pmcfg1 |=3D MX93_PMCFG1_RD_BT_FILT_EN;
> > +			break;
> > +		}
> > +	} else {
> > +		switch (counter) {
> > +		case 2:
> > +			pmcfg1 &=3D ~MX93_PMCFG1_RD_TRANS_FILT_EN;
> > +			break;
> > +		case 3:
> > +			pmcfg1 &=3D ~MX93_PMCFG1_WR_TRANS_FILT_EN;
> > +			break;
> > +		case 4:
> > +			pmcfg1 &=3D ~MX93_PMCFG1_RD_BT_FILT_EN;
> > +			break;
> > +		}
> > +	}
>=20
> how about
> 	u32 mask[] =3D { 	MX93_PMCFG1_RD_TRANS_FILT_EN,
> 			MX93_PMCFG1_WR_TRANS_FILT_EN,
> 			MX93_PMCFG1_RD_BT_FILT_EN
> 	      	     };
>=20
> 	if (couter >=3D2 && counter <=3D 4)
> 		event =3D=3D 73 ? pmcfg1 |=3D mask[counter - 2] :
> 			      pmcfg1 &=3D ~mask[counter - 2];

It seems ok for me. Will try this.

Thanks,
Xu Yang

>=20
>=20
> Frank
>=20
> >
> > -	pmcfg1 &=3D ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
> > -	pmcfg1 |=3D FIELD_PREP(PMCFG1_ID_MASK, axi_mask);
> > -	writel(pmcfg1, pmu->base + PMCFG1);
> > +	pmcfg1 &=3D ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF);
> > +	pmcfg1 |=3D FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask);
> > +	writel_relaxed(pmcfg1, pmu->base + PMCFG1);
> >
> >  	pmcfg2 =3D readl_relaxed(pmu->base + PMCFG2);
> > -	pmcfg2 &=3D ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
> > -	pmcfg2 |=3D FIELD_PREP(PMCFG2_ID, axi_id);
> > -	writel(pmcfg2, pmu->base + PMCFG2);
> > +	pmcfg2 &=3D ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF);
> > +	pmcfg2 |=3D FIELD_PREP(MX93_PMCFG2_ID, axi_id);
> > +	writel_relaxed(pmcfg2, pmu->base + PMCFG2);
> >  }
> >
> >  static void ddr_perf_event_update(struct perf_event *event)
> > @@ -514,7 +547,7 @@ static int ddr_perf_event_add(struct perf_event *ev=
ent, int flags)
> >  		ddr_perf_event_start(event, flags);
> >
> >  	/* read trans, write trans, read beat */
> > -	ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
> > +	imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
> >
> >  	return 0;
> >  }
> > --
> > 2.34.1
> >