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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org References: <20240305043952.21590-1-justin.swartz@risingedge.co.za> Content-Language: en-US From: =?UTF-8?B?QXLEsW7DpyDDnE5BTA==?= In-Reply-To: <20240305043952.21590-1-justin.swartz@risingedge.co.za> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Flag: yes X-Spam-Level: ************************** X-GND-Spam-Score: 400 X-GND-Status: SPAM X-GND-Sasl: arinc.unal@arinc9.com Hey Justin. I couldn't find anything on the MT7621 Giga Switch Programming Guide v0.3 document regarding which pin corresponds to which bit on the HWTRAP register. There's only this mention on the LED controller section, "hardware traps and LEDs share the same pins in GSW". But page 16 of the schematics document for Banana Pi BPI-R2 [1] fully documents this. The HWTRAP register is populated right after power comes back after the switch chip is reset [2]. This means any active link before the reset will go away so the high/low state of the pins will go back to being dictated by the bootstrapping design of the board. The HWTRAP register will be populated before a link can be set up. In conclusion, I don't see any need to disable the LED controller before resetting the switch chip. [1] https://wiki.banana-pi.org/Banana_Pi_BPI-R2#Documents [2] I've tested it on my MT7621AT board with a 40MHz XTAL frequency and a board with standalone MT7530 with 25MHz XTAL frequency. While the kernel was booting, before the DSA subdriver kicks in: - For the board with 40 MHz XTAL: I've connected a Vcc pin to ESW_P3_LED_0 to set it high. - For the board with 25 MHz XTAL: I've connected a GND pin to ESW_P3_LED_0 to set it low. Board with 40 MHz XTAL: [ 2.359428] mt7530-mdio mdio-bus:1f: MT7530 adapts as multi-chip module [ 2.374918] mt7530-mdio mdio-bus:1f: xtal is 25MHz Board with 25 MHz XTAL: [ 4.324672] mt7530-mdio mdio-bus:1f: xtal is 40MHz diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 51d7b816dd02..beab5e5558d0 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2216,6 +2216,15 @@ mt7530_setup(struct dsa_switch *ds) return ret; } + if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_25MHZ) + dev_info(priv->dev, "xtal is 25MHz\n"); + + if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ) + dev_info(priv->dev, "xtal is 40MHz\n"); + + if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) + dev_info(priv->dev, "xtal is 20MHz\n"); + id = mt7530_read(priv, MT7530_CREV); id >>= CHIP_NAME_SHIFT; if (id != MT7530_ID) { Arınç On 5.03.2024 07:39, Justin Swartz wrote: > Disable LEDs just before resetting the MT7530 to avoid > situations where the ESW_P4_LED_0 and ESW_P3_LED_0 pin > states may cause an unintended external crystal frequency > to be selected. > > The HT_XTAL_FSEL (External Crystal Frequency Selection) > field of HWTRAP (the Hardware Trap register) stores a > 2-bit value that represents the state of the ESW_P4_LED_0 > and ESW_P4_LED_0 pins (seemingly) sampled just after the > MT7530 has been reset, as: > > ESW_P4_LED_0 ESW_P3_LED_0 Frequency > ----------------------------------------- > 0 1 20MHz > 1 0 40MHz > 1 1 25MHz > > The value of HT_XTAL_FSEL is bootstrapped by pulling > ESW_P4_LED_0 and ESW_P3_LED_0 up or down accordingly, > but: > > if a 40MHz crystal has been selected and > the ESW_P3_LED_0 pin is high during reset, > > or a 20MHz crystal has been selected and > the ESW_P4_LED_0 pin is high during reset, > > then the value of HT_XTAL_FSEL will indicate > that a 25MHz crystal is present. > > By default, the state of the LED pins is PHY controlled > to reflect the link state. > > To illustrate, if a board has: > > 5 ports with active low LED control, > and HT_XTAL_FSEL bootstrapped for 40MHz. > > When the MT7530 is powered up without any external > connection, only the LED associated with Port 3 is > illuminated as ESW_P3_LED_0 is low. > > In this state, directly after mt7530_setup()'s reset > is performed, the HWTRAP register (0x7800) reflects > the intended HT_XTAL_FSEL (HWTRAP bits 10:9) of 40MHz: > > mt7530-mdio mdio-bus:1f: mt7530_read: 00007800 == 00007dcf > > >>> bin(0x7dcf >> 9 & 0b11) > '0b10' > > But if a cable is connected to Port 3 and the link > is active before mt7530_setup()'s reset takes place, > then HT_XTAL_FSEL seems to be set for 25MHz: > > mt7530-mdio mdio-bus:1f: mt7530_read: 00007800 == 00007fcf > > >>> bin(0x7fcf >> 9 & 0b11) > '0b11' > > Once HT_XTAL_FSEL reflects 25MHz, none of the ports > are functional until the MT7621 (or MT7530 itself) > is reset. > > By disabling the LED pins just before reset, the chance > of an unintended HT_XTAL_FSEL value is reduced. > > Signed-off-by: Justin Swartz > --- > drivers/net/dsa/mt7530.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c > index 3c1f65759..8fa113126 100644 > --- a/drivers/net/dsa/mt7530.c > +++ b/drivers/net/dsa/mt7530.c > @@ -2238,6 +2238,12 @@ mt7530_setup(struct dsa_switch *ds) > } > } > > + /* Disable LEDs before reset to prevent the MT7530 sampling a > + * potentially incorrect HT_XTAL_FSEL value. > + */ > + mt7530_write(priv, MT7530_LED_EN, 0); > + usleep_range(1000, 1100); > + > /* Reset whole chip through gpio pin or memory-mapped registers for > * different type of hardware > */