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Date: Fri, 8 Mar 2024 15:31:55 +0200
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Michal Simek <michal.simek@amd.com>
Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Mark Brown <broonie@kernel.org>
Subject: Re: [PATCH v1 3/3] spi: xilinx: Make num_chipselect 8-bit in the
 struct xspi_platform_data
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 <f7a882c8-5858-4d6b-8a70-0702c3170661@amd.com>
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On Fri, Mar 08, 2024 at 09:20:23AM +0100, Michal Simek wrote:
> On 3/7/24 16:43, Andy Shevchenko wrote:

..

> >   struct xspi_platform_data {
> > -	u16 num_chipselect;
> > -	u8 bits_per_word;
> > -	struct spi_board_info *devices;
> > -	u8 num_devices;
> >   	bool force_irq;
> > +	u8 num_chipselect;
> > +	u8 bits_per_word;
> > +	u8 num_devices;
> 
> all above have 32bits. It means on 64bit cpu you have 32bit gap here.

> > +	struct spi_board_info *devices;

On all architectures? I mean do all 64-bit architecture ABIs _require_
the pointer to be aligned at 8-byte boundary? Even if so, the struct
itself can be aligned on 4-byte boundary.

> It means this should be like this and then there is no gap between on
> 32bit/64bit systems.
> 
> struct xspi_platform_data {
> 	struct spi_board_info *    devices;              /*     0     8 */
> 	bool                       force_irq;            /*     8     1 */
> 	u8                         num_chipselect;       /*     9     1 */
> 	u8                         bits_per_word;        /*    10     1 */
> 	u8                         num_devices;          /*    11     1 */
> 
> 	/* size: 16, cachelines: 1, members: 5 */
> 	/* padding: 4 */
> 	/* last cacheline: 16 bytes */
> };

-- 
With Best Regards,
Andy Shevchenko