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AJvYcCV04dtsw9YuV8HZ/iNazD315DWjQkUeDmituA8MyBLpe5oGBjCkpqbOuo2TKXJYWyAcjQu8E96H2bEduv20471tk98NmgLVweaIPY7TBJMEFU/YtigIpcENzdauWxBULuS+kSSOCbK3O2GEfkGIicwd X-Gm-Message-State: AOJu0Yy7ygE7EFFIgp+qrSrHTnHxZlzP0ZonB3zRPTYSd+XGEcdqyhRN 26RVcJOLE5EPZmlWfqFCWk8PfNQV3n1FZ/qXjG0ZCKPHSfBK2CdSZARLTiJPgS2Gl9appAVfKSl lQH5lFLteqxVN5NmJAxkXsIPOYnA= X-Received: by 2002:a05:6512:3584:b0:513:8102:1a1e with SMTP id m4-20020a056512358400b0051381021a1emr2786397lfr.50.1709907193455; Fri, 08 Mar 2024 06:13:13 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240306165904.108141-1-puranjay12@gmail.com> <87ttlhdeqb.fsf@all.your.base.are.belong.to.us> In-Reply-To: From: Puranjay Mohan Date: Fri, 8 Mar 2024 15:13:02 +0100 Message-ID: Subject: Re: [RFC PATCH] riscv: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS To: Andy Chiu Cc: =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Paul Walmsley , Palmer Dabbelt , Albert Ou , Steven Rostedt , Masami Hiramatsu , Mark Rutland , Sami Tolvanen , Guo Ren , Ley Foon Tan , Deepak Gupta , Sia Jee Heng , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Song Shuai , =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Al Viro , Jisheng Zhang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-trace-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Hi Andy, > > > > I don't think implementing direct calls over call ops is fruitful for > > RISC-V because once > > the auipc/jalr can be patched atomically, the direct call trampoline > > is always reachable. > > Yes, the auipc/jalr instruction pair can be patched atomically just as > long as their size is naturally aligned on. However, we cannot prevent > 2 instructions from being fetched atomically :P > > > Solving the atomic text patching problem would be fun!! I am eager to > > see how it will be > > solved. > > I have a patch series to solve the atomic code patching issue, which I > am about to respin [1]. The idea is to solve it with yet another layer > of indirection. We add a 8-B aligned space at each function entry. The > space is a pointer to the ftrace entry. During boot, each function > entry code is updated to perform a load and then take the jump from > the 8-B space. When ftrace is disabled, we patch the first 4B-aligned > instruction to a jump so as to skip the ftrace entry. > > We are still discussing with Alex to see if we have a better way to do > it. If not then I'd update the patchset and re-send it. There's a > pending improvement in the series to reduce complexity. The 8-B > aligned space can be added before the function entry (just like your > patch). I briefly looked at the series and it looks promising. It looks similar to how BPF programs jump to trampolines on ARM64. If the choice has to be made about keeping the 8-B aligned space below or above the function entry and both choices are viable then I would prefer keeping the 8-B space below the function entry. I am saying this because when nops are added above the function entry clang's kcfi[1] doesn't work properly. Thanks, Puranjay [1] https://clang.llvm.org/docs/ControlFlowIntegrity.html#fsanitize-kcfi