Received: by 2002:ab2:3319:0:b0:1ef:7a0f:c32d with SMTP id i25csp614677lqc; Fri, 8 Mar 2024 07:07:33 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUp5yR7a9KTZYMxKAxIgyX2B0V35q4tkhKz5LO21Ub7HftcxUVbBHBRiF94nh7BScXLrokwwEUetBPZerfQAFkw5XzeFROMfqUk9oAK1w== X-Google-Smtp-Source: AGHT+IHstGTNkqqFg5LVRwtGSwZOxWt9D7azNokDnGpEYyn6Q97N2RNu84j8qQnuADVZUv5t7pvs X-Received: by 2002:a25:6c88:0:b0:dc6:6307:d188 with SMTP id h130-20020a256c88000000b00dc66307d188mr17338795ybc.25.1709910453167; Fri, 08 Mar 2024 07:07:33 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709910453; cv=pass; d=google.com; s=arc-20160816; b=as9XBssY0kRt0OtcheU12FYG3kYQ8DiNEz/SJkKU9K8LaDmqjhSwkTAHyJmQSYK3wH x4zSgYlk2RdXMUNSVa5r1zy1CjXjbBqWx3qr32+/IJiMwqkhtaW2l/hqgBycu/1dN60C baL8tFhIs/O8YAszEUGtMGaJ9FtqWL9I/4Cf9rx/rEaldeVyz2nNFmQnSAdfEdTuKMa8 NkzOg9VXQtC4U6OcI2d2YB5TFTwlxNPuiLrLJJJX8TEyOPx9lKalUVadMPxlP5CMTKoG MDFinID6esRUBUnp0GeeoCy0YnZJBQndxfGYOyNOcrt/JpTHxIIqx9RlOML93VPX9bjI uMbw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:date:subject:cc:to :from:dkim-signature; bh=4xYC1iqj/58M+RW0Zs2x67eh6obkIWMkt9il+46kMEE=; fh=TBJVee1avxckUsJNzSWQV9oVUJ5BvdrQLGVoVanefaE=; b=avqQ1N6eaWb4rtqfMd1+f+oKm4ynfmiNEw7JOyKv5NkWBgje3cBA69gaQ4tB/uY2P8 AmrmwneCASMJDhmg8dlxcgpKdk/G7ZNxa3ewy0sRKd8C8kz2xT4YwgiTHYDeK73Ao5sK 7U+mU6dOfHry5LQmcmXm7vSZ2SNeSNPJGrmA+GT4gHqrHs5tdK9K0xEXxPiWuNy5QLyF CZkP6EW5ySRADsx6CdyDGEMXyltMAMpOSA/KrrT2ftXCv3BGXgNumzwMHPxrGY5p1X6+ 1TBNlorj9dyCPWnmJ0jmlsjLWqbgVf+XMJmfVCxwgPWDZOxj+p59Owxrxf0jpEKjxSj/ yRTA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@efficios.com header.s=smtpout1 header.b=lqymgjoO; arc=pass (i=1 spf=pass spfdomain=efficios.com dkim=pass dkdomain=efficios.com dmarc=pass fromdomain=efficios.com); spf=pass (google.com: domain of linux-kernel+bounces-97213-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-97213-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=efficios.com Return-Path: Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id y70-20020a25dc49000000b00dcfc773ccedsi7927425ybe.136.2024.03.08.07.07.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 07:07:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-97213-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@efficios.com header.s=smtpout1 header.b=lqymgjoO; arc=pass (i=1 spf=pass spfdomain=efficios.com dkim=pass dkdomain=efficios.com dmarc=pass fromdomain=efficios.com); spf=pass (google.com: domain of linux-kernel+bounces-97213-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-97213-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=efficios.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id D0CAF1C21DE0 for ; Fri, 8 Mar 2024 15:07:31 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 31F6F1D68C; Fri, 8 Mar 2024 15:07:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=efficios.com header.i=@efficios.com header.b="lqymgjoO" Received: from smtpout.efficios.com (smtpout.efficios.com [167.114.26.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E69B11BF37; Fri, 8 Mar 2024 15:07:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=167.114.26.122 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709910441; cv=none; b=jRvs7RkaDeJnOQMgpPrEqx1MZLHil2gaCn1h9647M4r/ToAMnmlyQORQed7Ea/Gs2h0kPFHiFdZKK6V0ZIORZr2fuKZrRnS7kZBjD4y489gIxoFGHUl05RYsoFN6jCOFv8FTbZuKDeyoaK3KMz0/uFrZB+BD9YTZc/Kh3UNU3Rw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709910441; c=relaxed/simple; bh=cVFfc9GiI9uwQvvc+1EtU0M4+VVT4wxEv4PSJ/Z5oE0=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=rk29SGFXUqlDBeYCuw5aB6BildS5YQ9jDvu5o4jn5ydDRcqmaCE9abCeRJiJT5XPlud+szzlb8ZZvcbKtbEA9llv/QV/dSNQYsanOl16R43Lve4q+Bata3No072KSuMuX95rlXEAv+vL7qGIliWCHREVmxrkiI7m/IPTVrwWPz4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=efficios.com; spf=pass smtp.mailfrom=efficios.com; dkim=pass (2048-bit key) header.d=efficios.com header.i=@efficios.com header.b=lqymgjoO; arc=none smtp.client-ip=167.114.26.122 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=efficios.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=efficios.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=efficios.com; s=smtpout1; t=1709910436; bh=cVFfc9GiI9uwQvvc+1EtU0M4+VVT4wxEv4PSJ/Z5oE0=; h=From:To:Cc:Subject:Date:From; b=lqymgjoOEnp19WEbvh+oiQeuNIZ28AMyDXsM9gvrneELn7qlZUi/RuGXwQTifuP7G e9N/xZGx1tIhmKEYrJSXzuB9aJVlT0zd4B9fzatV477RAobdiv2k5N2ol3gdr6GlME 5H1Xa6PLqoIIcLybAgN96P8frK4d6QRlA+hpoMpq9Gg4gXdCr5B9VYDwgnLtfjRIX6 OYQrDo4Sszh5kBL97lC59+RQmxP5nJvNaBQ4x7FD2NMzsXmnduO5Yoj8SyylvDl3YD buurQyyO3MsbY+mjMmzYXqVwhuW4fNqOc0QrL/m6GGumY3TwvLKnWkbpFu87aZBVga klLCcSo65EuDw== Received: from thinkos.internal.efficios.com (192-222-143-198.qc.cable.ebox.net [192.222.143.198]) by smtpout.efficios.com (Postfix) with ESMTPSA id 4TrqK026JczgCR; Fri, 8 Mar 2024 10:07:16 -0500 (EST) From: Mathieu Desnoyers To: Ingo Molnar , Peter Zijlstra Cc: linux-kernel@vger.kernel.org, Mathieu Desnoyers , "levi . yun" , stable@vger.kernel.org, Steven Rostedt , Vincent Guittot , Juri Lelli , Dietmar Eggemann , Ben Segall , Mel Gorman , Daniel Bristot de Oliveira , Valentin Schneider , Catalin Marinas , Mark Rutland , Will Deacon , Aaron Lu Subject: [PATCH] sched: Add missing memory barrier in switch_mm_cid Date: Fri, 8 Mar 2024 10:07:19 -0500 Message-Id: <20240308150719.676738-1-mathieu.desnoyers@efficios.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Many architectures' switch_mm() (e.g. arm64) do not have an smp_mb() which the core scheduler code has depended upon since commit: commit 223baf9d17f25 ("sched: Fix performance regression introduced by mm_cid") If switch_mm() doesn't call smp_mb(), sched_mm_cid_remote_clear() can unset the actively used cid when it fails to observe active task after it sets lazy_put. There *is* a memory barrier between storing to rq->curr and _return to userspace_ (as required by membarrier), but the rseq mm_cid has stricter requirements: the barrier needs to be issued between store to rq->curr and switch_mm_cid(), which happens earlier than: - spin_unlock(), - switch_to(). So it's fine when the architecture switch_mm happens to have that barrier already, but less so when the architecture only provides the full barrier in switch_to() or spin_unlock(). It is a bug in the rseq switch_mm_cid() implementation. All architectures that don't have memory barriers in switch_mm(), but rather have the full barrier either in finish_lock_switch() or switch_to() have them too late for the needs of switch_mm_cid(). Introduce a new smp_mb__after_switch_mm(), defined as smp_mb() in the generic barrier.h header, and use it in switch_mm_cid() for scheduler transitions where switch_mm() is expected to provide a memory barrier. Architectures can override smp_mb__after_switch_mm() if their switch_mm() implementation provides an implicit memory barrier. Override it with a no-op on x86 which implicitly provide this memory barrier by writing to CR3. Link: https://lore.kernel.org/lkml/20240305145335.2696125-1-yeoreum.yun@arm.com/ Reported-by: levi.yun Signed-off-by: Mathieu Desnoyers Fixes: 223baf9d17f2 ("sched: Fix performance regression introduced by mm_cid") Cc: # 6.4.x Cc: Ingo Molnar Cc: Peter Zijlstra Cc: Steven Rostedt Cc: Vincent Guittot Cc: Juri Lelli Cc: Dietmar Eggemann Cc: Ben Segall Cc: Mel Gorman Cc: Daniel Bristot de Oliveira Cc: Valentin Schneider Cc: levi.yun Cc: Mathieu Desnoyers Cc: Catalin Marinas Cc: Mark Rutland Cc: Will Deacon Cc: Aaron Lu --- arch/x86/include/asm/barrier.h | 3 +++ include/asm-generic/barrier.h | 8 ++++++++ kernel/sched/sched.h | 20 ++++++++++++++------ 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/barrier.h b/arch/x86/include/asm/barrier.h index 35389b2af88e..0d5e54201eb2 100644 --- a/arch/x86/include/asm/barrier.h +++ b/arch/x86/include/asm/barrier.h @@ -79,6 +79,9 @@ do { \ #define __smp_mb__before_atomic() do { } while (0) #define __smp_mb__after_atomic() do { } while (0) +/* Writing to CR3 provides a full memory barrier in switch_mm(). */ +#define smp_mb__after_switch_mm() do { } while (0) + #include /* diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h index 961f4d88f9ef..5a6c94d7a598 100644 --- a/include/asm-generic/barrier.h +++ b/include/asm-generic/barrier.h @@ -296,5 +296,13 @@ do { \ #define io_stop_wc() do { } while (0) #endif +/* + * Architectures that guarantee an implicit smp_mb() in switch_mm() + * can override smp_mb__after_switch_mm. + */ +#ifndef smp_mb__after_switch_mm +#define smp_mb__after_switch_mm() smp_mb() +#endif + #endif /* !__ASSEMBLY__ */ #endif /* __ASM_GENERIC_BARRIER_H */ diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 2e5a95486a42..044d842c696c 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -79,6 +79,8 @@ # include #endif +#include + #include "cpupri.h" #include "cpudeadline.h" @@ -3481,13 +3483,19 @@ static inline void switch_mm_cid(struct rq *rq, * between rq->curr store and load of {prev,next}->mm->pcpu_cid[cpu]. * Provide it here. */ - if (!prev->mm) // from kernel + if (!prev->mm) { // from kernel smp_mb(); - /* - * user -> user transition guarantees a memory barrier through - * switch_mm() when current->mm changes. If current->mm is - * unchanged, no barrier is needed. - */ + } else { // from user + /* + * user -> user transition relies on an implicit + * memory barrier in switch_mm() when + * current->mm changes. If the architecture + * switch_mm() does not have an implicit memory + * barrier, it is emitted here. If current->mm + * is unchanged, no barrier is needed. + */ + smp_mb__after_switch_mm(); + } } if (prev->mm_cid_active) { mm_cid_snapshot_time(rq, prev->mm); -- 2.39.2