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AJvYcCVrIUDw7aZ1oWSlyX4ukSwXziAZdDCIt2XecgxorrII3+Rg8+nvSAuUS2C+ZhPRu5jtWcsDbSYcvpSd4yIXzt18Uj2LX57Tfw6npGO1OR1nGfWOf9n0jJBHx7c1WVYqwzMpR+6mzu/TNavIsw2rl+iNP1cLoBvWSPKr5j5SVEWnSsEnqhppL7iL6pipbsK9xAw+D3oWnDZ+OsOKXunZkjRprX0p2A6W X-Gm-Message-State: AOJu0YxQJsESJySnyvwv06zbYzN6AYGwXENZFKt8Wtkee7tfXGrHImjo ryCVyh0KN41ZBijXErSqnZ4YWxVcGVW5N1Y5OIxOmpIZ6r8E/ix8zgktrMVCfZRdW4b/1B+ciAO XVkyigUGi/FiRUBmmMKVCIBwteyZHMLjf X-Received: by 2002:a05:6122:4785:b0:4d3:499a:830c with SMTP id ee5-20020a056122478500b004d3499a830cmr557596vkb.13.1709931642864; Fri, 08 Mar 2024 13:00:42 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240308172726.225357-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240308172726.225357-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 8 Mar 2024 20:59:35 +0000 Message-ID: Subject: Re: [PATCH 4/5] i2c: riic: Pass register offsets and chip details as OF data To: Biju Das Cc: Geert Uytterhoeven , Chris Brandt , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Wolfram Sang , "linux-renesas-soc@vger.kernel.org" , "linux-i2c@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Fabrizio Castro , Prabhakar Mahadev Lad Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable >On Fri, Mar 8, 2024 at 6:15=E2=80=AFPM Biju Das wrote: > > > > Subject: Re: [PATCH 4/5] i2c: riic: Pass register offsets and chip deta= ils as OF data > > > > Hi Biju, > > > > On Fri, Mar 8, 2024 at 5:36=E2=80=AFPM Biju Das wrote: > > > > > > Hi Prabhakar, > > > > > > Thanks for the patch. > > > > > > > -----Original Message----- > > > > From: Prabhakar > > > > Sent: Friday, March 8, 2024 5:27 PM > > > > Subject: [PATCH 4/5] i2c: riic: Pass register offsets and chip > > > > details as OF data > > > > > > > > From: Lad Prabhakar > > > > > > > > With an increasing number of SoCs reusing this driver, each with > > > > slight variations in the RIIC IP, it becomes necessary to support > > > > passing these details as OF data. This approach simplifies the exte= nsion of the driver for other > > SoCs. > > > > > > > > This patch lays the groundwork for adding support for the Renesas R= Z/V2H SoC. > > > > > > > > Signed-off-by: Lad Prabhakar > > > > > > > > Reviewed-by: Fabrizio Castro > > > > --- > > > > drivers/i2c/busses/i2c-riic.c | 59 > > > > ++++++++++++++++++++++++++--------- > > > > 1 file changed, 44 insertions(+), 15 deletions(-) > > > > > > > > diff --git a/drivers/i2c/busses/i2c-riic.c > > > > b/drivers/i2c/busses/i2c-riic.c index > > > > 49a12f1ecdf9..3398d639b754 100644 > > > > --- a/drivers/i2c/busses/i2c-riic.c > > > > +++ b/drivers/i2c/busses/i2c-riic.c > > > > @@ -46,18 +46,6 @@ > > > > #include > > > > #include > > > > > > > > -#define RIIC_ICCR1 0x00 > > > > -#define RIIC_ICCR2 0x04 > > > > -#define RIIC_ICMR1 0x08 > > > > -#define RIIC_ICMR3 0x10 > > > > -#define RIIC_ICSER 0x18 > > > > -#define RIIC_ICIER 0x1c > > > > -#define RIIC_ICSR2 0x24 > > > > -#define RIIC_ICBRL 0x34 > > > > -#define RIIC_ICBRH 0x38 > > > > -#define RIIC_ICDRT 0x3c > > > > -#define RIIC_ICDRR 0x40 > > > > - > > > > #define ICCR1_ICE 0x80 > > > > #define ICCR1_IICRST 0x40 > > > > #define ICCR1_SOWP 0x10 > > > > @@ -87,6 +75,13 @@ > > > > > > > > #define RIIC_INIT_MSG -1 > > > > > > > > +#define RIIC_RZ_A_TYPE 0 > > > > > > > + > > > > +struct riic_of_data { > > > > + u8 family; > > > > > > Do you need family as compatible have this information? > > > > > Yes this is added to future proof it, as the RZ/V2H SoC has some bit di= fferences in the slave address > > register as compared to RZ/A and RZ/G2L. Comparing the family outside p= robe is not always preferred > > hence this is added as part of OF data. > > Ok. Got it. > But the family variable is unused and is wasting memory. > Simple reg layout is enough for device data?? > Ok, I'll drop it for the current implementation. Cheers, Prabhakar