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Subject: Re: [PATCH v11 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042
From: Stephen Boyd <sboyd@kernel.org>
Cc: Chen Wang <unicorn_wang@outlook.com>
To: Chen Wang <unicornxw@gmail.com>, aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, haijiao.liu@sophgo.com, inochiama@outlook.com, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, samuel.holland@sifive.com, xiaoguang.xing@sophgo.com
Date: Fri, 08 Mar 2024 18:15:12 -0800
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Quoting Chen Wang (2024-02-19 19:08:59)
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    clock-controller@10000000 {

This is the same address as the pll binding before this. How does that
work? It's the same register area as the pll node. The resulting DTB
should only have one compatible for this node.

> +      compatible =3D "sophgo,sg2042-rpgate";
> +      reg =3D <0x10000000 0x10000>;
> +      clocks =3D <&clkgen 85>;
> +      #clock-cells =3D <1>;
> +    };